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[FPGA] Synthesis using Synplify - HowTo disable retiming?

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nicoxp31

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fixgeneratedclocks

Hi,

I have some problems using Synplify Pro v8.8 for my FPGA design flow.
It seems that the tool enables retiming and pipelining register where as I ordered from the project file a disable of any retiming using the following set_options command:

#device options
set_option -technology VIRTEX5
set_option -part XC5VLX50
set_option -package FF676
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 0
set_option -use_fsm_explorer 1

#map options
set_option -frequency 25.000
set_option -run_prop_extract 1
set_option -fanout_limit 20
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3


Despite this, it seems that the tool retimed some registers:
##### BEGIN RETIMING REPORT #####

Retiming summary : 2 registers retimed to 20

Original and Pipelined registers replaced by retiming :
u_ww.u_wwww.u_www.clk_bit_o_0

New registers created by retiming :
u_ww.u_wwww.u_www.clk_bit_o_ret
[...............]

##### END RETIMING REPORT #####


Besides, I added into the code a synthesis macro in order to preserve the corresponding register from any eventual retiming using the following definition:
reg clk_bit_o /* synthesis syn_preserve = 1 */;

So what should i do in order that the tool does not remove this register (which is really important in my design btw)..??

Thanks a lot,
Regards,
Jerome
 

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