FPGA synthesis and false path

[sun_ray]

Is it necessary to set false path during FPGA synthesis? How can it be done if it is yes?

Regards

 

[K-J]

Is it necessary to set false path during FPGA synthesis?

Setting a false path is only necessary if the path truly is false and can never occur.

How can it be done if it is yes?

Consult the instructions for the FPGA synthesis tool that you are using.

Kevin Jennings

 

[StJo]

It depends strongly on your design if it is necessary or not
Some timing violations can be ignored, e.g. the hardware sets an register-bit but it doesnt matter if this bit is really set in the next cycle or some cycle later.
In that case you're allowed either to set a false path or a multicycle path

 

[rca]

defining false path is only required to meet the timing. if you could do without it's safer, because you are sure to not cut any unwanted path.