Sink0
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Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could not
find any driver that could be placed to run that multdrop network (any
protocol and datalink designed with small and size variable packet (Max 256
bytes) would be suitable) i designed one myself on a FPGA. On the on the
uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the
clock is recovered with oversampling the data (using the rise and fall edge
and a second clock with 90 degree phase as described in this paper:
**broken link removed**
.
The fisrt questions is: Is possible to implement such oversampling on a
CPLD? Does CPLDs got any kind of PLL or something like that?
Second: Do you think CPLDs are going to stay on the market for a long time?
Or they are going to disapear and there will be just FPGAs?
Third: This device must got a real small footprint. The best i found was a
EP1C3 of Altera, but any one knows how long is going to take until this
device is discontinued?
Any sugestion of using a CPLD or FPGA for this design, or sugestions of any
small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cable
of both and dont want to get a new one).
Thank you!
find any driver that could be placed to run that multdrop network (any
protocol and datalink designed with small and size variable packet (Max 256
bytes) would be suitable) i designed one myself on a FPGA. On the on the
uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the
clock is recovered with oversampling the data (using the rise and fall edge
and a second clock with 90 degree phase as described in this paper:
**broken link removed**
.
The fisrt questions is: Is possible to implement such oversampling on a
CPLD? Does CPLDs got any kind of PLL or something like that?
Second: Do you think CPLDs are going to stay on the market for a long time?
Or they are going to disapear and there will be just FPGAs?
Third: This device must got a real small footprint. The best i found was a
EP1C3 of Altera, but any one knows how long is going to take until this
device is discontinued?
Any sugestion of using a CPLD or FPGA for this design, or sugestions of any
small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cable
of both and dont want to get a new one).
Thank you!