FPGA max frequency question

[tariq786]

Hi,
I have synthesized a design in FPGA. According to synthesis report, it should run at 200 MHz.After place and route, when i do the post place and route (P&R) simulation with back annotation, it hardly runs at 50 MHZ (20ns) or (#10 clk = ~clk)

So can i safely say that 60 MHZ is the true frequency of the design or should i stick to synthesis estimate.

Moreover, with timing constraints such as period constraint of 10ns, P&R does not complain (it actually says, it has met the constraint). But when i do the post P&R simulation with back annotation, i get 50 MHZ or 20ns.

This is baffling me. Can someone throw light from his/her experience??

 

[RBB]

You should try to understand why the simulation(s) & STA runs are not aligning better.

 

[tariq786]

Ideally they should match. I dont know why are they not aligned. The only thing is that one is static and the other is dynamic.

Any hints or pointers????

 

[RBB]

What timing path is specifcally failing in the simulation?
Report that timing path in STA to determine where the discrepancy lies.

 

[Malek Lamari]

Hi,
the synthesis report indicate the max possible frequency.
Don't forget that in your board the reference clock is 50Mhz(crystal osci)
but this goes false if you use a frequency multiplier (PLL ..)
so, make sure of the reference clock used.