FPGA Low Power Design : Clock Gating or Asynchronous Reset

[elockpicker]

Hi everybody,

I'm involved with designing a low power system that has an embedded processor.
The processor is not active all the time hence clock gating might be a proper solution to reduce power consumption.
My problem is that the embedded microprocessor does not provide any type 'enable' signal and it only has an asynchronous reset.

Does asserting the (asynchronous) reset of this processor keep it from consuming power or I have to gate the clock?

More info:
FPGA : Actel Igloo Nano (AGLN250)
Embedded Processor : ABCCore (a simple embedded processor provided by Actel)

Thank you very much in advance.

 

[TrickyDicky]

gating the clock is usually a bad idea inside an FPGA.

 

[elockpicker]

you are right sir,
but this is a low speed design (main clock will be less than 15Mhz), and the synthesis tool is Synplify Pro (I think it can handle this situation very well).
Does asserting the (asynchronous) reset help lowering the power at all?

thank you

 

[mrflibble]

Does asserting the (asynchronous) reset help lowering the power at all?

Isn't that sort of thing in the datasheet? Without knowing the details of that gizmo I guess the answer would be "it depends".

 

[elockpicker]

I've read the datasheet : http://www.actel.com/ipdocs/CoreABC_HB.pdf
and didn't find much...
What kind of details should I be looking for?
and what is a 'gizmo' ?!?!

thanks

 

[bigdogguru]

I believe you mean CoreABC, rather than ABCCore.

Anyway, why not put the Igloo device to sleep?

Sleep Mode Power: Actel devices have a variety of sleep and standby modes that
reduce power to microwatts. IGLOO FPGAs implement Flash*Freeze mode, which
consumes as little as 5 μW while retaining the SRAM, register, and I/O information.

 

[elockpicker]

you're right, it's CoreABC
while the CoreABC is disabled the other modules store ADC samples to be further processed and then it CoreABC's turn ...
the device does goes to FlashFreeze mode but at other phases of system activity...

 

[bigdogguru]

Do the ADCs run continuously?

To be honest, I'm not very familiar with Actel's device, I mainly use Xilinx and Altera devices in my designs.

So, I would take a hard look at the datasheets and the CoreABC manual.

BigDog

 

[elockpicker]

Thank you for your interest.

The ADC supports the FPGA with samples at a rate of 500 samples/sec
FlashFreeze is a state (supported by some of Actel FPGAs) that the device retains it RAM and register content and still consumes very little power.
This mode is activated by FlashFreeze Pin.
Every time a sample is ready the ADC assert a 'Data Ready' signal which deasserts the FlashFreeze pin of the FPGA so it can read the sample.
After a specified number of samples are gathered, the FPGA processes them (at the point the CoreABC plays its role).
While samples are being collected the CoreABC has nothing to do thus it must be deactivated.

and I don't know how to disable a module lacking any 'enable' signals and with only an asynchronous reset.

 

[FvM]

Holdding all registers in reset will save most of dynamic power consumption of the device, only a smaller share of clock tree dynamic power consumption will be continued. In so far clock gating, or even better, disabling the clock conditioning circuit should slightly reduce the power consumption. If it's feasible depends on the design details.

 

[elockpicker]

so you confirm that keeping the asynchronous reset asserted cuts the clock tree at primary levels (so little power is consumed compared to not asserting the reset) ?
do you also confirm that this method is better than simply gating (ANDing) the clock in low speed designs?

 

[FvM]

It doesn't exactly cut the clock tree, it prevents the registers from switching. Clock gating at the global clock tree level should give sligthly better effect. If it's suitable for your design depend on the clock domain scheme which we can't know.

However, if the design is low speed, the dynamic power dissipation of the global clock tree most likely won't be high. If you want to know exactly, you should measure it yourself.