FPGA Logic Help Rising' Edge detection

[QUART]

Hello,

Can someone help me out, I am new to VHDL an I am trying to implement the following logic.

I have a 40ns high trigger pulse and a 25MHz Clock.

I need to trigger a control line high on detection of the 40ns pulse rising edge and
keep the control line high for 200 25MHz Clock cycles then drive the control line low at the end.

Any help or direction would be greatly appreciated. I am using Altera FPGA for first time with there tools.

Much thanks and Best Regards.

 

[sp]

i also a noob in this field... and am using Altera as well...

this is my code... u c whether u can understand....

the counter 'c' will count untill after 200 rising edge of the clk...

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity control is
   port(data_in, rst, clk, enable: in std_logic;
       control_line, data_out: out std_logic);
end control;

architecture control_arc of control is
begin

   process(data_in, rst, clk)
      variable c: integer;
      constant M: natural := 200;
   begin
      if rst = '1' then
         control_line <= '0';
         c:= 0;
      elsif rising_edge(clk) then
		if enable = '1' then
			c := c + 1;
			control_line <= '1';
	            if c = M then
		            c:= 0;
					control_line <= '0';
		            data_out <= data_in;
	            end if;
		end if;
      end if;
   end process;
end control_arc;

regards,
sp

 

[nand_gates]

Here is the code ur looking for...
Hope this helps!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pulse_stretcher is
  
  port (
    clk       : in  std_logic;
    reset_n   : in  std_logic;
    pulse_in  : in  std_logic;
    pulse_out : out std_logic);

end pulse_stretcher;

architecture behave of pulse_stretcher is
signal count : std_logic_vector(7 downto 0);
signal pulse_in_r, pulse_in_rr, pulse_in_3r : std_logic;
signal start_count : boolean;
signal pulse_out_int : std_logic; -- internal pulse_out
begin  -- behave

  pulse_sync: process (clk, reset_n)
  begin  -- process stretch_count
    if reset_n = '0' then               -- asynchronous reset (active low)
      pulse_in_r <= '0';
      pulse_in_rr <= '0';
      pulse_in_3r <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      pulse_in_r <= pulse_in;
      pulse_in_rr <= pulse_in_r;
      pulse_in_3r <= pulse_in_rr;
    end if;
  end process pulse_sync;
  
  start_count <= (pulse_in_rr = '1')  and (pulse_in_3r /= '1');
  
  stretch_count: process (clk, reset_n)
  begin  -- process stretch_count
    if reset_n = '0' then               -- asynchronous reset (active low)
      count <= (others => '0');
      pulse_out_int <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if start_count then
        pulse_out_int <= '1';
      elsif count = "11000111" then    -- count = 199 
        pulse_out_int <= '0';
      end if;
      if pulse_out_int = '1' then
        count <= count + 1;
      else
        count <= (others => '0');  
      end if;
    end if;
  end process stretch_count;
  pulse_out <= pulse_out_int;
end behave;

 

[soccer]

use bounded circuit to solve the detection problem

 

[QUART]

Thank you for your assistance, it is most appreciated.

Best Regards..

 

[dcbomb88]

Here is the code ur looking for...
Hope this helps!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pulse_stretcher is
  
  port (
    clk       : in  std_logic;
    reset_n   : in  std_logic;
    pulse_in  : in  std_logic;
    pulse_out : out std_logic);

end pulse_stretcher;

architecture behave of pulse_stretcher is
signal count : std_logic_vector(7 downto 0);
signal pulse_in_r, pulse_in_rr, pulse_in_3r : std_logic;
signal start_count : boolean;
signal pulse_out_int : std_logic; -- internal pulse_out
begin  -- behave

  pulse_sync: process (clk, reset_n)
  begin  -- process stretch_count
    if reset_n = '0' then               -- asynchronous reset (active low)
      pulse_in_r <= '0';
      pulse_in_rr <= '0';
      pulse_in_3r <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      pulse_in_r <= pulse_in;
      pulse_in_rr <= pulse_in_r;
      pulse_in_3r <= pulse_in_rr;
    end if;
  end process pulse_sync;
  
  start_count <= (pulse_in_rr = '1')  and (pulse_in_3r /= '1');
  
  stretch_count: process (clk, reset_n)
  begin  -- process stretch_count
    if reset_n = '0' then               -- asynchronous reset (active low)
      count <= (others => '0');
      pulse_out_int <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if start_count then
        pulse_out_int <= '1';
      elsif count = "11000111" then    -- count = 199 
        pulse_out_int <= '0';
      end if;
      if pulse_out_int = '1' then
        count <= count + 1;
      else
        count <= (others => '0');  
      end if;
    end if;
  end process stretch_count;
  pulse_out <= pulse_out_int;
end behave;

Hello,

anyone know why this code is written with 3 registers? is one register enough? for example just
start_count <= (pulse_in = '1') and (pulse_in_r /= '1');

 

[TrickyDicky]

it assumes the pulse in is asynchronous to the clock, so the first 2 registers remove any chance of metastability.