sydundar
Newbie level 5
I will deliver a FPGA IP core to one of my customer. But I dont have Enough Know-How to deliver.
I will give a compiled EDIF netlist. With this edif file customer can built his own design by writing a wrapper to it. But he wont be able to Pre-Synthesis and Post-Synthesis simulation He will just be able to Post Layout Simulation. Right?
To overcome this problem I am planning to deliver also mapped VHD Netlist. Using this file He will also be able to simulate all steps of his Design containing IP core. Right?
But If I give him additionally VHD Netlist. He will also be able to use Delivered Netlist (vhd netlist) with different Families, DIEs, Packages of FPGA's.
In all documents of Actel Synplify vhd netlist are for simulation purposes but i have tested They are also work in Hardwire.
- So I dont know exactly Which files i need to Deliver to my Customer?
- If vhd netlist can work on hardwire too , What is the differences of vhd and edif netlist?
Thanks for all your answers.
I will give a compiled EDIF netlist. With this edif file customer can built his own design by writing a wrapper to it. But he wont be able to Pre-Synthesis and Post-Synthesis simulation He will just be able to Post Layout Simulation. Right?
To overcome this problem I am planning to deliver also mapped VHD Netlist. Using this file He will also be able to simulate all steps of his Design containing IP core. Right?
But If I give him additionally VHD Netlist. He will also be able to use Delivered Netlist (vhd netlist) with different Families, DIEs, Packages of FPGA's.
In all documents of Actel Synplify vhd netlist are for simulation purposes but i have tested They are also work in Hardwire.
- So I dont know exactly Which files i need to Deliver to my Customer?
- If vhd netlist can work on hardwire too , What is the differences of vhd and edif netlist?
Thanks for all your answers.