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FPGA IP Core Deliverables To Customer

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sydundar

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I will deliver a FPGA IP core to one of my customer. But I dont have Enough Know-How to deliver.

I will give a compiled EDIF netlist. With this edif file customer can built his own design by writing a wrapper to it. But he wont be able to Pre-Synthesis and Post-Synthesis simulation He will just be able to Post Layout Simulation. Right?

To overcome this problem I am planning to deliver also mapped VHD Netlist. Using this file He will also be able to simulate all steps of his Design containing IP core. Right?

But If I give him additionally VHD Netlist. He will also be able to use Delivered Netlist (vhd netlist) with different Families, DIEs, Packages of FPGA's.

In all documents of Actel Synplify vhd netlist are for simulation purposes but i have tested They are also work in Hardwire.

- So I dont know exactly Which files i need to Deliver to my Customer?

- If vhd netlist can work on hardwire too , What is the differences of vhd and edif netlist?

Thanks for all your answers.


 

encrypted netlist as the deliverable instead of the RTL source code.
h**p://www.design-reuse.com/articles/18205/encrypted-netlist.html
 

I have been delivered IP cores that are just the verilog files from Synplify.
I used these files for pre-layout simulation (mapping the device library) and for synthesis.
The only problem is that they are targetted to a specific device: I cannot change device family (maybe, tweaking the file, I may change device).
 

Hello , i want to send data to my ethernet controller on my
FPGA(cyclone) board of Altera.
What algorithm of sending data via this interface ?? What first steps i
need to do in order to accomplish this mission. Maybe someone can advise
me some book that can help me in this project.
Thanks.
 

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