fpga implementation of circuits having clock

[jincyjohnson]

if we want get a pattern that is changed in ach clock cycle, how can we run in spartan 3E fpga kit. plz reply

 

[jincyjohnson]

for circuits having clock, whether we have to use a clock divider for imlementing the circuit in fpga.if so, can u plz explain.

 

[TrickyDicky]

Please explain what?
You write RTL, you compile the design and you load it onto the FPGA and run it.

You question is rather vague, if you're a software programmer, it's like asking:

I want a C program for my CPU. How do I do that?

 

[jincyjohnson]

I am using vhdl coding for a sequential circuit. The implementation will be done using spartan 3EXc3s500E. If we use the clock frequency of the fpga kit, we cant view the pattern change during each cycle, since the clock frequency of the kit is 50 MHz. So how can we view the output at each clock cycle.plz reply

 

[TrickyDicky]

what are you trying to view this cycle on? An LED would be updated too fast, so you would need to slow the clock down (generated clock enables perhaps)? But chipscope would allow you view the sequence at 50 MHz, as would some comms to a PC.

 

[jincyjohnson]

i want to giv a frequency of 1Hz from 50 MHZ. can u please giv the code. if the input clock 0f 50 MHz is given as clk1 and output of 1 Hz is denoted as clk2, which clock is used in main program

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i didnt connect to the kit. I think the clock frequency can be changed by clock wizard in the xilinx core generator. but if i open the xilinx core genertaor then the clocking wizard is inactive.what is the reason

 

[verylsi]

You can use 50 Hz as an input clk and try to derive a second clock from DCM, Else you can design your own clock divider using a simple counter.

in your program you can use the main clk (50 Hz ) and with edge detection of 2nd clock(1 Hz ) inside the main clock, you can check the output .

As far as your second question is concerned , clocking wizard is inactive or option to chose 2nd clock is inactive, can you send a screenshot of your DCM where it is inactive ?

 

[jincyjohnson]

The clock divider code is as follows

[/CODE]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity c1 is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end c1;
architecture arch of c1 is

signal counter: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,counter,reset)
begin
if(reset='0') then counter<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then counter <=counter+1;
if (counter = 12000000) then temp <= NOT temp; counter<=0;
end if;
end if;
CLKout <= temp;
end process;
end arch;[/HTML]

The main program is

library ieee;
    use ieee.std_logic_1164.all;
    
    
    
    entity pattern_generation is       
        port( clock : in std_logic;
              B_in  : in std_logic_vector(0 to 7);             
              C_in  : in std_logic;
              pattern_out : out std_logic_vector(0 to 7) );
        end pattern_generation;
        
        
    architecture ar of pattern_generation is
        
        component Recon_JC is
        port(clk2 : in std_logic;
             rst  : in std_logic;             
             mode_sel : in std_logic_vector(1 downto 0); 
             Jn_in    : in std_logic_vector(0 to 7);            
             Jn_cw    : out std_logic_vector(0 to 7)             
             );
         End component;
        component accumulator_cell is        
        port( clock    : in std_logic;
              set      : in std_logic_vector(0 to 7);
              reset    : in std_logic;
              c_in     : in std_logic:='0';
              B_in     : in std_logic_vector(0 to 7);
              Pattern  : out std_logic_vector(0 to 7) );
          end component;
        
        signal count_out : std_logic_vector(0 to 7);
        signal temp:std_logic_vector(0 to 7):="00000000";
        signal mode_sel:std_logic_vector(1 downto 0):="00";
        signal rst:std_logic:='1';
        --signal count:integer:=0;
        begin
            process(clock)
                variable count:integer:=0;
                begin
                    if rising_edge(clock)then
                        count:=count+1;
                        if rst='1'then
                            mode_sel<="00";
                            rst<='0';
                            count:=0;
                            elsif count=0 then
                                mode_sel<="10";                                
                                elsif count>=1 and count<=9 then
                                    mode_sel<="01";
                                    elsif count>9 then
                                        mode_sel<="10";
                                        count:=1;
                                    end if;
                                end if;
                            end process;
                        

            S00: Recon_JC port map(clock,rst,mode_sel,temp,count_out);          
            S01: accumulator_cell port map(clock,B_in,rst,C_in,count_out,pattern_out);
            
        end ar;

So in main program whether i use clock, clk2 etc or the output of the clock divider CLKout. plz rply

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when the clock wizard is is open i got this screen. what are the next steps. plz reply.

 

[ads-ee]

The clock divider code is as follows

[/CODE]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity c1 is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end c1;
architecture arch of c1 is

signal counter: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,counter,reset)
begin
if(reset='0') then counter<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then counter <=counter+1;
if (counter = 12000000) then temp <= NOT temp; counter<=0;
end if;
end if;
CLKout <= temp;
end process;
end arch;[/code]

Bad idea making clocks from counters in the logic fabric. FPGA's have very limited access to the global clock buffers from the logic fabric. The placement of the clock driving flip-flop can vary from build to build unless you lock down the placement of that flip-flop. Even then the routing can vary depending on the placement of other logic around the area. The only time it might be a good idea is if it is the only clock used in a design and the input clock is only used to run the counter. This would still mean that the clock generated from the counter must be considered as asynchronous to the input clock and anything from outside the FPGA.

Also I suspect you don't realize that you are actually counting 12,000,001 times between toggling CLKout, which gives you a period of 24,000,002 CLKin clocks. Common mistake of the inexperienced.

            S00: Recon_JC port map(clock,rst,mode_sel,temp,count_out);          
            S01: accumulator_cell port map(clock,B_in,rst,C_in,count_out,pattern_out);

Oh, how I detest instantiated components done with positional associations, what happens if you change the order of the ports in the component declaration. Opps the design doesn't compile...
Always use named association so the connections are explicitly defined. This seems to be the norm for teaching VHDL/Verilog in the university system. Shows how little they know about the real world application of engineering and maintenance of a product years after it was developed.

when the clock wizard is is open i got this screen. what are the next steps. plz reply.

Did you read the user guide for the core. It tells you step by step what all the tabs and the items on those tabs mean.


Regards

 

[mrflibble]

Oh, how I detest instantiated components done with positional associations, what happens if you change the order of the ports in the component declaration. Opps the design doesn't compile...

You are being faaaar too optimistic. Of course the swapped port design will compile. It will just give you a result that is completely wrong, and you will spend many hours wondering whyyyyyy, oh whyyyyyyy??!?

I am all for the OP using positional port associations. Then he can learn from his pain and suffering, and after the fun debug excercise that is bound to happen he will vow to never ever EVAH use positional port associations again. As long as I don't have to work on any of his code, this is the way to go. XD

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Did you read the user guide for the core. It tells you step by step what all the tabs and the items on those tabs mean.

This is worth repeating ... twice:
Did you read the user guide for the core. It tells you step by step what all the tabs and the items on those tabs mean.

The "Datasheet" button in core generator is pretty useful. Pops up a PDF with all sorts of handy information.

 

[layowblue]

Many people here are patient and friendly. But it does not mean we can squander the resource.
Please do you home work a little, just a little. Understand the basic concept of FPGA, read the spec. Then ask questions that you thought of, tried to resolve but failed.

A hint: never ask for "code". Instead, pasting a code you designed, and ask for review or debug is much more acceptable. At least, it means you did try to resolve the problem.