[FPGA] How to reduce Hold errors ?

[nicoxp31]

hold violation fpga

Hi,

After having used the traditional design flow on Xilinx ISE tool (FPGA Virtex-5), i have still some hold timing violations.

Here is one example:

Timing constraint: TS_XXXXX = PERIOD TIMEGRP "XXXXX" 166 ns HIGH 50%;

167 items analyzed, 15 timing errors detected. (0 setup errors, 15 hold errors)
Minimum period is 3.550ns.
--------------------------------------------------------------------------------
Hold Violations: TS_XXXXX = PERIOD TIMEGRP "XXXXX" 166 ns HIGH 50%;
--------------------------------------------------------------------------------
Hold Violation: -2.349ns (requirement - (clock path skew + uncertainty - data path))
Source: XXXX/gap_cnt[3] (FF)
Destination: XXXXXX/gap[1] (FF)
Requirement: 0.000ns
Data Path Delay: 0.911ns (Levels of Logic = 2)
Positive Clock Path Skew: 3.225ns
Source Clock: XX.cmil[7] rising at 0.000ns
Destination Clock: YY/clk13_rf_cl_i_0 rising at 166.000ns
Clock Uncertainty: 0.035ns

Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

So all my timing violations are due to some positive clock path skew and the clock path skew is much bigger as the data path delay.

SO here are my questions in order to remove these HOLD Violations:
- Should i play rather on synthesis or PAR options?
- Is it normal that clock path skew delay is much bigger than the data path delay?
- How should I play with the (SDC or UCF) constraints options in order to reduce this?

Thanks a lot,
Jerome

 

[echo47]

positive clock path skew

The clock should have relatively low skew, not 3.225ns. See "Global Clock Tree Skew" value in the data sheet.

Be sure the clock is routed on a dedicated clock distribution network, rather than through ordinary routing paths. The place-and-route software usually auto-detects the clock signal and infers a global clock buffer, but sometimes I have to instantiate the buffer myself. One way to examine the clock net is to open the layout (NCD file) in FPGA Editor and highlight the clock net.

 

[nicoxp31]

hold errors

The synthesis tool (synplify) recognized the clock signal since it created a clock buffer but i am not sure that the place-route tool detected it.
In the UCF file which is the "link" between synthesis and place-route tools (ISE tool) timing constraints, should I insert a special command for this clock buffer in order that the tool does recognize them correctly ?
Usually in this case , what do you try to look at first ?
Thanks, Jerome

 

[echo47]

fpga hold error

I just noticed a problem:

Source Clock: XX.cmil[7] rising at 0.000ns
Destination Clock: YY/clk13_rf_cl_i_0 rising at 166.000ns

I think that means your source and destination flops (gap_cnt[3] and gap[1]) are using two different clock signals. That's very bad, unless this is special logic for crossing clock domains. If it is clock-domain-crossing logic, then you need to apply different timing constraints to it.

I think the HDL synthesis tool, such as XST and Synplify, is what generates or doesn't generate the clock buffers. The place-and-route tools just follow the netlist provided by the HDL synthesizer.

I don't have much experience with Synplify.