fpga floating point problem!!!

[Indrajit Ghosh]

hi,
I am trying to write a code which will recieve real values from the real time enviroment.but verilog does not support real value synthesis, so how will i write a code in such situation,i don't want a truncated form of the real number suppose 2.3145 >2(this i don't want).

so how do i process real value in the codeE?

 

[FvM]

Instead of the abstract real type, synthesizable logic uses float or fixed point numbers. Read about it!