Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

FPGA driven by external clock

Status
Not open for further replies.

ttse7

Junior Member level 2
Joined
Mar 7, 2006
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,447
I have got a altera stratix II dsp board and built a nios softcore cpu inside. I try to drive the fpga using a clock from a external hardware. My problem is the clock form external hardware cannot drive the PLL inside the fpga.

When I monitor the clock to be input to fpga, the duty cycle is varied but meaured frequency is still 66MHz. Now, nios sometimes fails to work due to the external clock.

Experts, can you help?

I can use the clock to drive the nios by using fpga built-in clock without any problem. My project needs fpga to work with this external hardware. How to incorporate two hardware with two different clocks?
 

Iouri

Advanced Member level 2
Joined
Aug 17, 2005
Messages
682
Helped
87
Reputation
174
Reaction score
8
Trophy points
1,298
Activity points
4,814
Cut the trace from external osc and put desired osc, or you you can use PLL component from SOPC builder, and use "original" osc
 

mmarco76

Member level 5
Joined
Jan 4, 2008
Messages
85
Helped
6
Reputation
12
Reaction score
0
Trophy points
1,286
Activity points
1,937
Have you put the external clock in a input of the the PLL?
Depending on the exactly device some pins are specified to be the one that enter in the PLL.
Have a look on the Stratix2 pdf and then cut the trace of the clock and wire it to the right pin.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top