FPGA Design using MATLAB simulink

[membership]

hi all, I want to implement Sgma-Delta ADC on FPGA altera board using verilog code; I want to design my circuit using MATLAB simulink and then use MATLAB HDL coder to get verilog code ; but i dont know how to design my circuit in MATLAB and HOW to start with MATLAB; any body have useful document to satrt designing sigma delta ADC in MATLAB?
thanks in advance

 

[ninju]

**broken link removed**

https://www.math.osu.edu/~overman.2/matlab.pdf

There are many other similar tutorials on MATLAB. Regarding sigma delta, you might find a lot of help from matlab central.

 

[membership]

tnx ninju i installed sigma delta toolbox (delsig) and insert in to my Matlab software toolboxes, but i can not see this tool box among them !! and dont know how to open it?
any guidance very appreciated....

 

[ninju]

I need more details on what you did, also which version of MATLAB you're using.

One more word of caution, last time, when i used the HDL coder, it gave an un-synthesizable VHDL code. I don't know how it'll be for verilog.

 

[membership]

I need more details on what you did, also which version of MATLAB you're using.

One more word of caution, last time, when i used the HDL coder, it gave an un-synthesizable VHDL code. I don't know how it'll be for verilog.

my MATLAB Software is R2011b(7.1). I download DSToolbox.rar then unzip it and copy the folder of delsig to the directory of MATLAB toolbox then from file>set path>Add folder/Add subfolder>"choose delsig">ok>close

unsynthesizable code?!!! oh... so do you have any experience of using ALtera DAP Builder in MATLAB?

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my MATLAB Software is R2011b(7.1). I download DSToolbox.rar then unzip it and copy the folder of delsig to the directory of MATLAB toolbox then from file>set path>Add folder/Add subfolder>"choose delsig">ok>close

unsynthesizable code?!!! oh... so do you have any experience of using ALtera DAP Builder in MATLAB?

sorry Altera DSP Builder Blockset i mean..

 

[ninju]

I haven't used the Altera one as such. It was a filter generated using matlab's vhdl coder that caused a problem and was un-synthesisable. You'd better ask someone else about this. I have a much much older version of matlab. I doubt its supported anymore.