fpga design flow question

[cmos babe]

hi,
what i know is that synthesis is the process of transforming behavioral description of hardware into a netlist of logic primitives and mapping is the process of mapping the logic to the target resources(LUT's,MUX's..etc) is that right?

what's confusing me is that when i click the "view RTL schematic" process in ISE i get a schematic whose components are LUT's resources. shouldn't this be available after mapping ?

 

[nand_gates]

You are right!!!
For generating the RTL view you require some symbol library! As a short
cut methode ISE uses LUT's symbol library!!
Use SyplifyPro you will see the difference in RTL view and netlist view!

 

[cmos babe]

hey nand_gates,
i made a mistake , the view rtl schematic process shows logic gates while view technology schematic generates the one with LUT's and they are different schematics, but this is still confusing because I thought that the LUT's and other resource utilization should occur in the mapping process, or maybe it's just an initial guess by the synthesis tool representing the "Device utilization summary" given by the synthesis log file....

 

[FLEXcertifydll]

Go to try SyplifyPro in FPGA design flow, which is the standar flow in FPGA domain.
Also, on the view of myself, Debussy is also powerful tool for RTL code debug. and a very wonderful tool for cross debug; it will reduce ur developing cycle.

 

[vryaag]

See there are to types of libraries that every synthesizer uses if you use the technology libraries then you will get the LUT's which you are talking about else if you are using the primitives then you will be gettting the gates. which you think you should be getting.
to avoid getting that change the libraries to priomitives you will get what is required,

 

[phoenixfeng]

because the synthesis tool do with design for certain target resources,

mapping is putting the netlist into the real fpga chip
in fpga design flow ,before mapping ,the netlist include LUT, etc , then in mapping process put the LUTs into the real FPGA chip