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FPGA Decoupling Doubts

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May 23, 2011
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As an EMC measure, we need decoupling capacitors for each power supply pin for any ICs. Especially for high-speed circuit controlled by FPGA, clean voltages prevent abnormal performance of the circuit.

Usually decoupling capacitor is connect in such a way: power to gnd via a capacitor. From AC viewpoint, this capacitor acts as a short circuit for high frequency noise to go flow back to the power supply without affecting the circuit.

One thing I don't understand is power to power bypass capacitor.
What kind of EMC measure is this?

Say if there's a noise existed on 2.5V, since the capacitor acts as a short between 2.5V and 1.8V. Isn't it these two voltages shorted accidentally for a short period of time?

Or to create a low impedance path in between these two planes so that the noise will flow back to the power supply side via ground ultimately??


It is correct the capacitor acts as a conductive device in the AC context. But it is one of the features of capacitor. The main reasons of decoupling capacitor is to eliminate (or reduce) inductance of traces of PCB in high frequency.
So it clears, why the decoupling capacitors should be placed near the power pins, due to we don’t want to have another inductive path after the capacitor.
The Xilinx UG203 is discussed about this subject.

One thing I don't understand is power to power bypass capacitor.
It's not a usual measure in my opinion. Where do you see it?
You'll possibly see particular circuit nodes that are bypassed to a supply node rather than ground. But very unlikely for FPGA supplies.

I have never seen power to power decoupling, what I have seen though are stitching capacitors, when signals cross a split between two voltage planes in an adjacent power plane. This should be used as a last resort when routing if possible, and you add the capacitors either side of the offending route.
If someone has put capacitors between voltages on the schematic for decoupling purposes they are WRONG, the problem is that these caps will couple high frequency noise between the planes. Hence using them to stitch planes together is only recomended as a last resort.
Refer to Henry Ott 'Electromagnetic Compatability Engineering' Pages 621-632
I found it in my project. I think I need to refer to the circuit designer for further detail indeed.
I totally agree with Marce. One thing for sure is when there's a high frequency noise on 2.5V plane, this capacitor will certainly play a good role as a low impedance path to conduct the noise to the 1.8V plane.

What about ferrite bead placed in between two voltage plane?
As I know, at low frequencies say <100kHz, ferrites are inductive; thus they form a low-pass LC filters with capacitors in power supply. Above 100kHz, ferrites becomes resistive, blocking high frequency signal.
So it is really important to have ferrite bead in between voltage planes?
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I've just referred to the circuit designer for further details on having capacitor in between of different voltage levels.

The explaination is as follow: As we know, it acts as a return path for signal to cross the split of two voltage planes. Since this involves large amount of signal traces, they viewed it as a block and apply one capacitor on the board to connect two voltage planes together.

This absolutely different from what we have learnt. I doubt that there's a fundamental error here. For multilayer board, which reference layer do we refer our signals to? From the explanation above, it seems that both Gnd plane and PWR plane are treated as a reference at the same time. For outer layer signal, return path is usually referred to GND layer. For inner layer signals, we can either refer it to PWR plane and GND plane. Since GND plane is filled entirely on the plane, and it is also the common for all the voltage levels, why not we just make the GND layer as our universal reference? This is where our concept usually get confused easily, regarding which layer to be used as a reference? I personally think that this capacitor has rendered no help for achieving uniform return path, but in fact increase the risk of noise conduction in between different voltage levels, causing unstable voltage supply for IC.

So another doubt arises here, some people might think that there are enough decoupling capacitors next to the IC, therefore the conduction of noise by capacitor won't cause any troubles to the IC. I personally think that this concept abides our rules of designing for EMC. This capacitor may end up as a culprit of noise source before playing its main role as return path for signal crossing different power planes.

Refer to the ppt file for clearer image of my explanation and understanding.


  • Image.ppt
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Please refer to this link for further discussion of stitching capacitor's effect on the board: **broken link removed**

Stitching capacitor only works effectively at low frequencies. So for noise occurrence on particular voltage plane due to SSO, I think this capacitor might worsen the noise margin by providing a low impedance in between power planes.

Firstly, I have not heard of capacitor being used between two power planes.
If your translating signal voltage levels in your PCB from one level to another it should be done with a buffer IC (digital signals only not power signals) not at the PCB level.
Besides which, if it is a FPGA board you will also experience higher noise levels in your signals. Since your power plane return path is not through ground. So the drop it sees between voltage levels...which is weird.

The only place I have seen such a thing are with precompensation circuits to a LVDS circuit.

By referring to the link above, for a 4-layer board, stitching capacitor is to provide a return path for the signal trace if it crosses split between two power planes.
And it also mentioned that the stitching capacitor does not work well at high frequency, I wonder this capacitor could be removed.

Again for the definitive view on stiching capacitors refer to:
Refer to Henry Ott 'Electromagnetic Compatability Engineering' Pages 621-632
The stiching capacitors are only used where signals cross splits in power planes, and this is only a problem when the signal layer is coupled (ie the layer next to it) to the power layer and thus this power layer is being used for the signals return current. The problem is you can only determine and place these capacitors when the board is layed out as they are only effective within a certain distance of where the track crosses the split.
It is quite counter intuative to think of return currents using power planes instead of ground planes, but if the power planes are the neares layer the signal returns will use this path of least inductance. When the return hits a split it has to do a round trip to power supply and back on to the next plane area.
Nelsonys, I would suggest you ask the circuit designer to read the Henry Ott chapter mentioned above, I think they are being a bit optomistic in treating these signal as a block. You would be better adding extra gound plane(s) to provide a clean signal return. The signal return path is as important as the signal, for Si and EMC. Even with one capacitor the return currents will still have to meander around the board.
Yes I agree with you Marce.

By the way, if this stitching capacitor fails to do its job as a return current if the signal crosses a split, will it act as a conducting path for noise across power planes?

As Henry Ott says this should be a last resort. What we do is if a signal has to cross a power plane split then we make sure only lowish speed signals or analogue signals cross any splits, and only if we cannot route them another way. I have seen quite 3V3 areas split from the main 3V3 by a pi filter and then capacitors put across the split because of signals, negating the use of a pi filter!!:)

Usually people put a ferrite bead to create an even cleaner 3V3 from the main 3V3. The problem here is, with such stitching capacitor put so far away from those block of signals, I doubt it will just worsen the case, because the capacitor would possibly conduct high frequency noise from 3V3 to 2V5. Could you confirm about this?

Another question is say a 8 layer stackup:
1 - signal
2 - GND
3 - signal
4 - PWR
5 - PWR
6 - signal
7 - GND
8 - Signal

The return for layer 3 signal would be GND (layer 2) or PWR (layer 4)? I think it would be GND of layer 2, since it can provide a low impedance, uniform return path for the layer 3 signal, coupling of EM field will be better on GND layer. Am I right?

The return for layer 3 signal would be GND (layer 2) or PWR (layer 4)?
The truth is, you can't arbitrarily choose a return path. The return current will split to both planes. By deciding to layout a power supply node as a plane, you make it suffcient low impedant to "attract" return currents of adjacent signal traces like a ground plane. A power plane with many distributed bypass capacitors to ground can play this role in most cases. But you have a problem with high level, single ended digital signals, e.g. clocks. They will at least excite some standing waves at the planes and may cause radiated emissions elsewhere. To get completely rid of it, you would need to have the signal embedded between two ground planes and via fences all along the trace.
Is it the reason why the stitching capacitor appears in this case? Since the return EM field will split to both ground and power plane, how am I going to layout a large bunch of signals passing through split power planes below with GND plane above it? There's no better location to place the stitching capacitor also.

It's kind of unintuitive indeed...

I see you are now getting to grips with what it is like for a PCB designer doing high speed layout, IMPOSSIBLE:sad:
What we have to do is weigh up all the possibilities and options and come up with the most suitable in terms of Signal Integrity, EMC etc. As FvM siad , you cant choose where a return current will flow, but you can influence it. But more on that later.
I would like to question your stack up, as I think with the current stack up you will have more problems with power supply noise, Simultaneous switching noise and EMC problems, these will also reduce your signal integrity. I would strongly recomend that you have a GND layer closely coupled (dielectric 0.1mm for FR4) with each power supply layer. This is of more importance initialy than where your signals are going to couple. You need clean power supplies, first, if they are going to be noisy, the rest of the layout will be noisy. Again Henry Ott, Electromagnetic Compatability Engineering, section * layer stack ups is again an excellent reference. If you havn't got it (buy it, it is invaluable) I would suggest this stack up from this book.

Low Frequency signals, Components
High Frequency Signals
High Frequency Signals
Low Frequency signals, Components

This gives the best compromise, the low frequency signals dont realy mind crossing power plane splits (this is compared to high frequency signals, that do mind crossing the splits), closely coupled power pairs, and contigous ground planes next to high speed signals.

Some stuff on Simultaneous switching noise.
**broken link removed**
**broken link removed**

Anyway its a Sunday here so I gonna do somthing other than PCB's for a few hours:-D
Have Fun
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I do not have very solid concept on how actually PCB stackup can affect power supply noise, SSN and EMC.
The PCB stackup is decided as a standard of my company for 8 layer-stackup. And I found this a really common PCB stackup for 8-layer PCB.

Now here's the constraint for the current board that I'm designing now. This is a small board with layer-3 and 6 densed with impedance-controlled traces. And I have order not to make big modification (including stackup) on this board as the circuit designer did not receive any EMI feedback by now. Layer-6 has the most critical problem of crossing different power plane splits, that's why the circuit designer prepared stitching capacitors for this purpose.

I do not have any idea on how to mitigate this problem appropriately because these stitching capacitor only work well on certain distance according to Henry Ott, and my main difficulty is insufficient board space.

Is there any solution to mitigate this problem without changing stackup?

Secondly, if these signals are low-speed signal, should I get rid of these stitching capacitors?
I still believe these inappropriately-placed stitching capacitor will cause EMC problem somehow...
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Refer to the attachment for clear image of my description.


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  • Lay-5_6.bmp
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Quick reply:
Interesting, as I have always done and more often seen boards with closely coupled power plane layers. With todays fast rise times and high speed designs I prefer the closely paired planes (0.1mm dielectric), but I now insist that the signal layers are coupled to a contigous ground plane as well, so our layer counts are now 10-12 instead of 8 and 14-16 instead of 10, so we can optimise the designs. This is on our high speed designs, on less challenging we still use the paired planes, but have more freedom with the signals. It keeps the power plane inductance down with a closely couple ground plane, and in future we are looking at 0.05mm between planes to give us good planar capacitance.
A couple of links:
Page 27 of the following document has a description of plane inductance and its importance for todays fast switching times.

H. Ott notes on PCB stackup, this is a small part of Chapter 16, from his book Electromagnetic Compatability Engineering.
PCB Stack-Up - Introduction

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