vandelay
Advanced Member level 4

fpga as sdram
I am in a situation where I need a powerful coprocessor to take care of large sets of algorithm expressions (the algorithm lines are in a repetative form with different values, think block IIR filter). I have my eyes on the new Spartan-6 devices, with their DSP48A1 blocks for algorithm power and integrated memory blocks for storage of the input and output values.
Now, my processor has an unused external bus interface (16 or 32-bit wide data, upto 25 bits of address IIRC, differential clock, 1.8V or 3.3V). I am thinking I'll interface the FPGA to the processor's unused bus interface as it would provide a pretty decent bandwidth.
I am thinking a flow like page writing the input variables to FPGA block RAM, then writing some trigger/message into a dedicated command/control block RAM area of the FPGA initiating the algorithm (could be as simple as two huge lists of 128-bit fixed point numbers i wanted multiplied in pairs), then make the FPGA trigger an external interrupt to the processor telling the algorithm has completed, and lastly reading the data back from a result block RAM, again as if the FPGA was SDRAM.
I am pretty noob on FPGAs so I don't have experience enough to trust my system design thoughts on this matter, could anyone give me a heads up on this method? Is such an SDRAM "slave" interface a complex undertaking?
I am in a situation where I need a powerful coprocessor to take care of large sets of algorithm expressions (the algorithm lines are in a repetative form with different values, think block IIR filter). I have my eyes on the new Spartan-6 devices, with their DSP48A1 blocks for algorithm power and integrated memory blocks for storage of the input and output values.
Now, my processor has an unused external bus interface (16 or 32-bit wide data, upto 25 bits of address IIRC, differential clock, 1.8V or 3.3V). I am thinking I'll interface the FPGA to the processor's unused bus interface as it would provide a pretty decent bandwidth.
I am thinking a flow like page writing the input variables to FPGA block RAM, then writing some trigger/message into a dedicated command/control block RAM area of the FPGA initiating the algorithm (could be as simple as two huge lists of 128-bit fixed point numbers i wanted multiplied in pairs), then make the FPGA trigger an external interrupt to the processor telling the algorithm has completed, and lastly reading the data back from a result block RAM, again as if the FPGA was SDRAM.
I am pretty noob on FPGAs so I don't have experience enough to trust my system design thoughts on this matter, could anyone give me a heads up on this method? Is such an SDRAM "slave" interface a complex undertaking?