kingearlkwan
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Hi,
I want to design an FPGA project that is an alarm clock on which it will alarm every 1.5hrs. setting the FPGA to 24hr clock using 7segment display seems to be no problem and I can make it. However my problem is how will I output a sound every 1.5hrs since I don't have any idea how to use the audio codec on fpga board that i'm using.is someone have an idea how to do it? I'm using a verilog HDL for my code and DE1 altera board. I have a deadline to meet and all your help is are greatly appreciated. thanks.
I want to design an FPGA project that is an alarm clock on which it will alarm every 1.5hrs. setting the FPGA to 24hr clock using 7segment display seems to be no problem and I can make it. However my problem is how will I output a sound every 1.5hrs since I don't have any idea how to use the audio codec on fpga board that i'm using.is someone have an idea how to do it? I'm using a verilog HDL for my code and DE1 altera board. I have a deadline to meet and all your help is are greatly appreciated. thanks.
