AMCC
Member level 2
Hi,
I’m a newbie on VHDL (and on Advantage also )
I’m using FPGA Advantage 6.2 and I’m trying to use VHDL configuration file to select the desired architecture for synthesis.
My configuration file is:
configuration top_entity_config of top_entity is
for struct
for all : reg
use entity pci_acp.reg(v1_0);
end for;
end for;
end top_entity_config;
I’m trying to use architecture v1_0 of the entity reg of the library pci_acp. The problem is that architecture v1_1 (from reg and also on library pci_acp) is ‘set as default’ and when generating the script files v1_1 is called instead of the architecture defined in the configuration file.
I hope you can help me.
Thank you in advance.
Best Regards
AMCC
I’m a newbie on VHDL (and on Advantage also )
I’m using FPGA Advantage 6.2 and I’m trying to use VHDL configuration file to select the desired architecture for synthesis.
My configuration file is:
configuration top_entity_config of top_entity is
for struct
for all : reg
use entity pci_acp.reg(v1_0);
end for;
end for;
end top_entity_config;
I’m trying to use architecture v1_0 of the entity reg of the library pci_acp. The problem is that architecture v1_1 (from reg and also on library pci_acp) is ‘set as default’ and when generating the script files v1_1 is called instead of the architecture defined in the configuration file.
I hope you can help me.
Thank you in advance.
Best Regards
AMCC