Force Synopsys DC to use multi fanin gates

[noropuck]

Hello everyone,

I am trying to compile a VHDL code to Verilog so that using another script I can generate a specific circuit format (not for running on any hardware though). My main objective is to use as many multi fanin gates like AND3_X2 and above to minimize the circuit depth. Right now, DC only gives me AND2_X2 and nands or nors no matter how I modify the NangateOpenCell library. How should I tell the compiler to prefer these gates and merge as many as possible? This is not my main area of expertise so it might be a noob question but I appreciate any help or resources. Thanks!

 

[ThisIsNotSam]

The compiler will always pick cells that it considers to be more efficient. Your AND3 doesn't look attractive to it, for whatever reason. Longer delay, high power, higher area.

One more thing: these are not "multi fanin" cells. These are just cells with multiple inputs. There is nothing special about them.

 

[noropuck]

Hi, I've customized my library w.r.t area and leakage power. I want DC to only use AND and XOR not OR or INV. I set the area for OR and INV to very big numbers but still DC uses them. How can I force it not to use those gates?

 

[ThisIsNotSam]

set_dont_use

 

[noropuck]

set_dont_use

It won't compile then, because synthesis requires AND, OR, INV.

 

[ThisIsNotSam]

do a first pass of the synthesis, then apply set_dont_use directive, and then run an incremental synthesis pass. maybe the tool will replace all INVs for other logic.

 

[noropuck]

Where can I find a good resource that explains these commands and compile flow? Is the user guide the only resource?

 

[ThisIsNotSam]

Where can I find a good resource that explains these commands and compile flow? Is the user guide the only resource?

there are also tutorials on the internet