noropuck
Newbie
Hello everyone,
I am trying to compile a VHDL code to Verilog so that using another script I can generate a specific circuit format (not for running on any hardware though). My main objective is to use as many multi fanin gates like AND3_X2 and above to minimize the circuit depth. Right now, DC only gives me AND2_X2 and nands or nors no matter how I modify the NangateOpenCell library. How should I tell the compiler to prefer these gates and merge as many as possible? This is not my main area of expertise so it might be a noob question but I appreciate any help or resources. Thanks!
I am trying to compile a VHDL code to Verilog so that using another script I can generate a specific circuit format (not for running on any hardware though). My main objective is to use as many multi fanin gates like AND3_X2 and above to minimize the circuit depth. Right now, DC only gives me AND2_X2 and nands or nors no matter how I modify the NangateOpenCell library. How should I tell the compiler to prefer these gates and merge as many as possible? This is not my main area of expertise so it might be a noob question but I appreciate any help or resources. Thanks!