Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Force PI and Measure PO

Status
Not open for further replies.

vikasec089

Newbie level 3
Joined
Aug 27, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bengaluru
Activity points
1,294
can anybody explain in detail the concept of force PI and Measure PO, also tell me the advantage of measure PO in ATPG patteren verification
 

During the capture phase, you could cover or not the non scan I/O pad with this force PI (before clock pulse of capture), and capture PO after the clock capture pulse.
This will cover the combinational logic between the non scan pad (PI) and the first flops, and the logic between the flop and the Output pad (PO)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top