If a design has no outputs, then it has no purpose. If there are no outputs, then resource usage will always = 0, regardless of corner case.
If you are referring to leaving outputs unconnected, then yes, you can force the fit in both Altera and Xilinx, but the XIlinx option is a bit of a fudge.
Altera/Intel: assign all outputs you want unconnected to virtual pins. Then they will remain in place when fitted.
Xilinx - you have to connect the outputs to a pin or they will be removed. Xilinx does not offer virtual pins.