For reset signal why use active low rather than high?

[sweesw]

use of active low reset

The question may sound naive but I think there are some other reasons than just convention.

 

[edavio]

active low conventions

Guess it is for anti-jamming, as we always pull-up reset signal.

 

[papyaki]

Hi,

Remember also that it is easier to hold an open collector output to a low state during power supply start up.

 

[realtek]

I think it's anti-noise issue in the beginning,
if active high
then any glitch(noise) will reset the system
but at present , all system has debounse ckt to avoid this,
so it become a history issue .

 

[alphi]

For start-up power of you systerm,use low reset signal can get some delay,when power get to reliable,reset pin go to high voltage.

 

[falling_stone]

Hi,
I think it came from old and dark times of 5V TTL logic when HIGH level had higher noise margin, thus there was lower chance to get a low-going glitch on the reset input putting the whole system to undesirable reset during the normal work. For the same reason were made active-low write/output enables, chip selects, DMA requests, etc.
Regards,
F.S.

 

[delay]

Hi,

By convention most ASIC and IC designers use active low signals across the board primarily to conserve power during valid signal assertion.

delay

 

[whizking]

from TTL an open is treated an a HIGH. so is the connection to reset is not given or it becomes open by chance it should not reset the system. hence active low signal seems a gud option.
any views are encouragingly welcomed.

 

[giggs11]

This is related very closely to the design of standard cells or circuits using the various logic design techniques. For static for example, the circuits are easily realized if an active-low signal is used for the reset.

 

[echo47]

Another reason ... In the days of TTL, a low input consumed more power than a high input, so it was nice to have high signals wherever possible.

 

[Arthurzss]

I add one...the cells use active low reset are smaller than the cells use active high reset.

 

[tom123]

because The most of DFF cell that TSMC and other vendor provided have

active low reset input, perhaps active reset logic can be simpler than

active high reset logic.

The question may sound naive but I think there are some other reasons than just convention.

 

[nemolee]

Because the power is from off to on, and the level is from low to high.
So the reset signal is better for low, not high.
This is my opinion.
Thanks.