I think it's anti-noise issue in the beginning,
if active high
then any glitch(noise) will reset the system
but at present , all system has debounse ckt to avoid this,
so it become a history issue .
Hi,
I think it came from old and dark times of 5V TTL logic when HIGH level had higher noise margin, thus there was lower chance to get a low-going glitch on the reset input putting the whole system to undesirable reset during the normal work. For the same reason were made active-low write/output enables, chip selects, DMA requests, etc.
Regards,
F.S.
from TTL an open is treated an a HIGH. so is the connection to reset is not given or it becomes open by chance it should not reset the system. hence active low signal seems a gud option.
any views are encouragingly welcomed.
This is related very closely to the design of standard cells or circuits using the various logic design techniques. For static for example, the circuits are easily realized if an active-low signal is used for the reset.