For loop Problem in Verilog

[masab_ahmad]

Hi all,

I am having trouble with this code. Xa, Bi, Y, Bj, Z and W are I/Os of another module which multiplies and adds Xa-Z to give the output W, which works fine alone. The loop variable seems to be working fine too as correct values are assigned to the variable new1. The problem arises when Xa-Z are assigned values, all the values assigned to Xa are only those on index 5 of new1 and same is the case for variables Y, Z and W.
Maybe the multiplication takes time and the loop doesn't wait for it and moves on to the next index.
Please help!





always@(posedge clk)
begin
if(calc_strt==15)
begin
for(i=0;i<6;i=i+1)
begin
if(calc<15)
begin
mul_en <= 1;
new1 <= {Xodd[9],Xodd[9], Xodd[9], Xodd[9], Xodd[9], Xodd, 5'b00000}; //Go1
Xa<=new1;
Bi<=A0; //A0 is a constant
Y<=Xeven;
Bj<=0;
Z<=0;
Go1a <= W[15:5];
calc <= calc + i;
end
else
begin
calc <=calc;
mul_en <= 0;
end
end
end

 

[FvM]

Behaviour as expectable. That's how a for loop works. The iteration is performed in one clock cycle, only the last assigned value is visible outside the loop.

 

[masab_ahmad]

is there a way by which i may get the values at the other indices, maybe without the for loop?

 

[FvM]

The answer depends on the intended operation of the other module which isn't said unfortunately.

Basically you have two options:
- pull the code inside the for loop, either directly or as a function. The hardware equivalent of this code is instantiating 6 modules in parallel, the calculation code must work without a clock.
- perform the calculation sequentially by replacing the for loop with a state machine. The calculation will take at least one clock cycle per index value, possibly more if required by the calculation. The method is particularly useful for lengthy calculation with large resource requirement, e.g. dividers, floating point math.

 

[masab_ahmad]

I think the second option you have specified is better for a reduced hardware, many thanks for the help!