for loop in verilog is synthesizable or not..............

[dipin]

hi,

i had a verilog code that contains two for loops.The code works fine and it is synthesizable(checked using xilinx ISE 14.4)

this is my code

 for(i=0 ; i<N ; i=i+1) begin 
 
 if(yin[i+1] < 0 ) begin

   xin[i+2]  <= xin[i+1]  -  yin[i+1] ;
   yin[i+2]  <= yin[i+1] +  xin[i+1]  ;

   end else begin

   xin[i+2] <= xin[i+1] + yin[i+1] ;

   end
 
end

its a pipelined operation.
my question is is there any probem if use a for loop in verilog???
did all the tool and FPGA support for loop??

thanks & regards

 

[TrickyDicky]

You have to remember that loops are unrolled during compile time. So this means the loops will unroll into parrallel hardware, or serial hardware, depending on the behaviour of the code. You're safer here because you have non-blocking asignments, and so you get a pipeline. Using blocking assignments would have given you a long logic chain when yin is less than 0.

What this code produces is a mux for each value value of x selecting between the two possible values. For the yin values, it should just create a clock_enable using the compare.