for loop in verilog code

[gnoble29]

I have written a verilog code using 'for' loop..My aim is to display 2,3,4 in three consecutive clock cycle.But for the first clock cycle itself,my 'for' loop is executing fully and showing output as 4.How can I avoid this??
(I studied that for loop will execute sequentially only.But I am not getting output sequentially.)
I am including my code below...Plz help me...



module for_test(clk,n,m); //programe for testing the for loop

input clk;

output [7:0] m;
output n;

reg [7:0] m;
integer n;

always @(posedge clk)

begin
for(n=2;n>=0;n=n-1)

begin
if(n==2)
begin
m <=8'h02;
end

else
if(n==1)
begin
m <=8'h03;
end
else
if(n==0)
begin
m <=8'h04;
end
end
end
endmodule

 

[TrickyDicky]

you have to remember that for loops unroll into parrallel hardware. So in your case on each rising edge of the clock the whole for loop executes. So at the end of a clock edge, m will be 4. You need to use a counter that increments on the clock edge. for loops should not be used often.

 

[gnoble29]

ok..then how can i modify the above program so that the for loop will
execute only one iteration for each clock.....
PLZ help me....thanks for ur reply

 

[rberek]

TrickyDicky already gave you the answer. For loops in Verilog are used to produce parallel hardware, and do not execute in the same way that a software for loop would. Describe a hardware counter and use its values to generate your output.

r.b.

 

[gnoble29]

TrickyDicky already gave you the answer. For loops in Verilog are used to produce parallel hardware, and do not execute in the same way that a software for loop would. Describe a hardware counter and use its values to generate your output.

r.b.

Actually above code is only a sample...I want to include a block of
statements in each iteration that i want to execute sequentially in each
clock cycle..If i go for state machine i want to replicate my code for
each state and code length become very large...Thats why i am asking
about for loop that execute sequentially like a state machine!!!

 

[sureshaa]

hi gnoble29,

I didnt understand one point. whether For loop is necessary in your design?
If it is yes,you can't increment using clock edge.Because the for loop increment operation is not depend on the clock.
If it is no, Design a simple down counter buddy!!!

 

[TrickyDicky]

Actually above code is only a sample...I want to include a block of
statements in each iteration that i want to execute sequentially in each
clock cycle..If i go for state machine i want to replicate my code for
each state and code length become very large...Thats why i am asking
about for loop that execute sequentially like a state machine!!!

There is no such thing.

I suggest you delete your code, and get a peice of paper. Draw the circuit you're trying to create. Only when the circuit is correct can you write the HDL. HDL stands for hardware description language, so if you dont know the circuit, how do you expect to describe it?

 

[sureshaa]

To optimize the code I suggest you one. Just check the conditions and assert a signal whenever it is satisfied.Then check that signal cond and assign your outputs. As you have common outputs, you can check n of different conditions.

- - - Updated - - -

The above appro will reduce the no of lines. And will reduce the repeated lines. Instead of State machine replace with two if statements. But the thing is careful about the latches and "sequences( May be use fllags)"..

 

[gnoble29]

hi gnoble29,

I didnt understand one point. whether For loop is necessary in your design?
If it is yes,you can't increment using clock edge.Because the for loop increment operation is not depend on the clock.
If it is no, Design a simple down counter buddy!!!

In my design all the iterations of for loop is executing in one clock edge....
I want a for loop which will execute one iteration in one clock edge...That means in first rising edge of clock,it should execute first iteration of for loop.In second rising edge of clock,it should execute 2nd iteration of for loop like wise it should continue....
thanks for ur replies!!!!

 

[mrflibble]

I want a for loop which will execute one iteration in one clock edge...That means in first rising edge of clock,it should execute first iteration of for loop.In second rising edge of clock,it should execute 2nd iteration of for loop like wise it should continue....

So use a counter. And most importantly, as TrickyDicky already suggested: throw the current design in the bin. Get a fresh piece of paper and work out the logic design.