Hi
I am having a little trouble with loops as well.\
I am interested in getting samples of a an arbitrary waveform from an external signal using a simple D flip flop. (mind it that the incoming waveform signal is unknown)
So what I am doing is, that I need to sample the incoming waveform for only one second and see what is that shape of the incoming signal during this one second period. I have the internal clock running at 50MHz on the FPGA board and I am using this clock to sample the incoming signal pulses. So whenever the clock is high, I simple sample the input waveform to output. But I want to have some control over the timing. I mean I want to do this sampling only for one second.
After I have sampled the incoming signal for one second, i will repeat the same procedure for next one second and so on and so forth.
I am having a trouble coding it in VHDL. Can someone help me on this please?