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FOR !error: generic or port clause in a block statement is not supported! thanks !

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rudder

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FOR help !error: generic or port clause in a block statement is not supported!

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b:in std_logic;
cin: in std_logic;
co: out std_logic;
s: out std_logic);
end full_adder;
architecture rtl of full_adder is
begin
example:block
port (a_A:in std_logic;
a_B: in std_logic;
a_Cin:in std_logic;
a_Co:eek:ut std_logic;
a_S :eek:ut std_logic);
port map(a_A=>a,a_B=>b,a_Cin=>cin,a_Co=>co,a_S=>s);
signal tmp1,tmp2:std_logic;
begin
p1:process(a_A,a_B)
begin
tmp1<=a_A xor a_B;
end process p1;

p2:process(tmp1,a_Cin)
begin
tmp2<=tmp1 and a_Cin;
end process p2;

p3:process(tmp1,a_Cin)
begin
a_S<=tmp1 xor a_Cin;
end process p3;

p4:process(a_A,a_B,tmp2)
begin
a_Co<=tmp2 or (a_A and a_B);
end process p4;

end block example;
end rtl;
 
Last edited:

You have some text starting with "example:block" that shouldn't be there.
 

like the error says - your compiler does not support block statements. Use processes instead.
 

more likely it doesn't support the port/port-map feature of blocks. It is a strange feature in VHDL. Basically the code in the block becomes an ad-hoc entity. It has ports which are connected to the port map. This can be used to allow the block to be copied easily (basically, as if it were an instance of an entity). Blocks can be useful, but are overall a rare construct. I typically use them when I have signals that are local to a handful of things, and I want to declare them near where they are used.
 

not solved ,but thanks everyone who viewed the topic!
 

not solved ,but thanks everyone who viewed the topic!
In the present code, there's no real purpose of a block statement. It can be omitted, if you rename some signals or use alias definitions for it.
 

not solved ,but thanks everyone who viewed the topic!

The only solutions is to move away from blocks, or find a compiler that supports block ports (I dont think there are any).
 

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