[SOLVED] For clock crossing FIFO why don't the signals empty & full goto both clock domains?

[matrixofdynamism]

For clock crossing FIFO why don't the signals empty & full goto both clock domains?

Here is a picture of the Dual Clock FIFO used to "transmit multi-bit signals from one clock domain to another" and it is "usually implemented as a wrapper around a dual port RAM". It is from a book.



It is not clear to me when exactly are the signals full and empty asserted. Why does signal full only goto the "write clock domain" and empty only goto the "read clock domain"?

I mean, the write clock domain may know when to stop writing because of the full signal, but how does it know when to start writing again since it does not get the empty signal?
Similarly, the read clock domain gets the empty signal so it knows when to stop reading, but it does not get the full signal so how does it know when to start reading?

 

[UltraGreen]

Re: For clock crossing FIFO why don't the signals empty & full goto both clock domain

As Full and empty signals are flags, writing will start as soon as the full flag goes low.
and reading starts again as soon as empty flag goes low.

Now when to set these flags high and low depends on what logic has been used. there are multiple ways to do that though.

 

[vGoodtimes]

Re: For clock crossing FIFO why don't the signals empty & full goto both clock domain

for the simple case, "full" only matters in the write-domain as a way to stop overflows. "empty" only matters in the read domain to stop underflows.

For the write side, there is no reason to look at empty -- if you ever see full = false you know you can write data NOW!

For the read side, there is no reason to look at full -- if you ever see empty = false you know you can read data NOW!

 

[matrixofdynamism]

Re: For clock crossing FIFO why don't the signals empty & full goto both clock domain

aha, so that is how it works. I thought that once the FIFO was filled in the writer waited until it was empty before filling it to full again.

 

[shaiko]

Re: For clock crossing FIFO why don't the signals empty & full goto both clock domain

aha, so that is how it works. I thought that once the FIFO was filled in the writer waited until it was empty before filling it to full again.

You can design logic around the FIFO that does just that. And it may even make some sense for some application.
But the overall throughput of such a system will be less then half of "write as long as not full / read as long as not empty".

 

[ads-ee]

Re: For clock crossing FIFO why don't the signals empty & full goto both clock domain

aha, so that is how it works. I thought that once the FIFO was filled in the writer waited until it was empty before filling it to full again.

A specific example of doing something like this is when you have a pcketized interface and you need to perform data transfers in a burst. In this situation you would enable the FIFO read count or a programmable level flag to indicated when the burst can start.