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For an analog designer, what is your design methodology?

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D2004

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When a design project is assigned to you, how do you start and finish it?
Do you think what good methodologies should be?
 

Dear rfic
The paper that you introduce is the basic analog
paper on california university?
I think that D2004's meaning is how to plan the
design when a project is assigned to you?
The problem is very difficult to answer?
 

Analog_design did catch my meaning.

Since there are many experienced analog guys in this forum, I'd like to know their design methodologies. For example, if you are assigned to design a bandgap, or LDO, or ADC, how do you plan, start, and finish it in good quality?
 

Hi D2004,

I think whatever analog circuits you will design, you must familar with the basic analog sub circuits, such as opa, comparator, current or voltage bias and generator . and you can start with them.

Best Regards
Analog_starter
 

modeling is a good technique as the first step if you have been assigned a new project.
 

There have many fields in analog circuit design, such as RF, ADC, and etc. I think there have different design methodology to do the relevent project.

However, i agree with Btrend, modeling is a very important step for an analog designer. To design a good analog circuit, a good modeling for the devices is essential, especially in designing analog IC (CMOS, BiCMOS, etc.) operates at high freq.
 

1. Understand the application for the product
2. Draw a block diagram of your product
3. Design from the bottom-up (transistor to system level)

The key for me is to break everything into small chunks.
 

Yes, I agree with johnsmith101. Circuit design would certain be much easier if you separate it into block diagram. From that you can design subcircuit such as comparator , amplifier and so on.
 

I think it is very important to know everything you can about analog subsystems that currently exist so you don't end up wasting time re-designing things. For example, there are a number of ways of implementing a bandgap reference.

As was mentioned, designing by breaking down the design into subsystems is essential as it will reveal many instances where circuits can be re-used with minor modifications.

If you have access to an analog guru, you can probably learn much more in a shorter period of time than any book can teach you.

Best regards,
v_c
 

Dear rfic,

Which specific informantion on boser's website is related to the design methodology of analog ic design?

Thanks.
 

for me the method is similar to science research method..

1. Given a spec...

2. Literiture Review

3. Top Level Sytem Design...usally in block diagram using MATLAB. Setting the block to get the spec.

4. Then every block is eleborate at schematic level. Making the netlist. Run simulation to test the funcionallity. Merge all block schematic and compare the result with top level and spec.

5. If ok, then go down to LAyout drawing. Run DRC, LVS and gain the parasitic extraction.

6. Parasitic data collected and DSP analysis run using MATLAB to meet spec.

7. If all is ok...then tape out


7 step but take a very long time to complete and many obstacle

Added after 10 minutes:

for me the method is similar to science research method..

1. Given a spec...

2. Literiture Review

3. Top Level Sytem Design...usally in block diagram using MATLAB. Setting the block to get the spec.

4. Then every block is eleborate at schematic level. Making the netlist. Run simulation to test the funcionallity. Merge all block schematic and compare the result with top level and spec.

5. If ok, then go down to LAyout drawing. Run DRC, LVS and gain the parasitic extraction.

6. Parasitic data collected and DSP analysis run using MATLAB to meet spec.

7. If all is ok...then tape out


7 step but take a very long time to complete and many obstacle
 

it is useful for my disign,thanks.
 

I like Syukri's methodology, you can tell he is really a circuit designer with practical experience. Although my flow is similar, let me explain my approach.

1) Definition - A good definition will make or break your product. In this phase, you move from an idea (I want a very fast ADC) to a list of specifications, targeted towards a practical application. How fast? How accurate? What is the Vcc? The signalling? Who will use it? What are the competing products on the market? How much will it cost to make? How much can we sell it for? How can we add value to either raise performance or lower cost to ensure our product will be a winner? Market research and customer feedback are extremely important in this stage - it may be the most painful stage in terms of time, effort, arguments ;-), and compromise but if done correctly you will have customers banging on your door demanding your product!!

2) Concept - From your list of specifications, you now build a rough estimate of your plan to implement these specs. Here you use macro simulations with ideal components, or Matlab, etc to show your approach will work. Invite all the other designers to your concept review - show them that your approach will meet or exceed the definition and let them tear it apart looking for problems. Don't skip this, too many designers "fall in love" with their own ideas and get misled because they like some approach and cannot see that it may not be the BEST approach. Probably the second most painful phase since you must come up with some tangible way to meet an agressive set of specs and prove it to a tough audience

3) Block Level - Now that the overview of the part and each block is complete in an ideal case, each of those blocks must be completed and able to satisfy their criteria in a practical implementation. I stand firmly behind the theory that if each block is solidly defined from a top level, and each block meets those definitions from the bottom level, your IC is guaranteed to work when you finally assemble the blocks. Here you will be calculating offsets, considering sizing, ratios, current draw, temperature, and process in order to build blocks that fulfill your top-level concept. You should be able to replace blocks of your concept simulation with actual circuit blocks and get the same results.

4) Top Level - If you are replacing your macro blocks one-by-one, this is done for free as you progress! However, sometimes your chip has several channels or some other factor that is not addressed while you are building blocks. Now the full chip with ESD protection is built and simulated over the typical and extreme operating conditions. You should be able to provide a simulation for each item in your spec table, along with all safe operating area criteria like thermal shutdown and current limiting for example. It's best to check several parameters at once since the simulation times are so long!! Now is a good time to catch up on your reading and movies as the simulator runs for two days per test - good thing you have accurately defined and tested these low level parameters as debugging will be very easy! You certianly don't want to burn two days worth of work because your blocks aren't interacting as you wanted them to!!

5) Layout. I assume you have a layout engineer that will be doing the physical implementation - assist him! Or better, do it yourself!! Consider what is critical - make notes on matching, cross-coupling, noise sensitive and noise insensitive lines and review each block as it is laid out! Parasitic analysis is probably OK for small circuits, but 5k or 10 FET in analog? It's going to be a month-long sim!
10% of your circuit will be 90% of your parasitic problems - know what is sensitive or noisy and pay extra attention to these blocks!

6) Validation - The final, most important step of all! When the silicon comes back, you must verify that all your circuit parameters are correct. Maybe not the bias in every transistor, but references, critical signal paths, operation over the entire input and temp range, and all the other precision specs must be checked by hand on the bench and at ATE. Make sure that your chip meets your spec table, and have 30-100 devices tested over temp to check the distributions of your parameters and trends of these parameters over temp and input voltage. Make friends with your ATE engineer, you're going to be spending a lot of time together as you help him design his tests and correlate his results to your hand-tested results from the bench.

7) Evaluation - If your device doesn't pass, you will need to do a revision and go back to step 6. Once your device passes validation, give it to your applications engineer and let him torture it in all the demanding, practical applications he can think of. Since you have already tested the part over much more demanding conditions you should have no problem here. There's nothing more embarrassing than if someone else finds a bug that you yourself should have screened and fixed during validation. At the end of this phase, your applications engineer should have sent sample boards to all the top customers who will be demanding devices ASAP!

8) Release & Support. Sometimes things go wrong - be prepared to revisit a device if the yield goes haywire at a later date. Good thing you kept all your notes from Validation, you can easily sit down and do tests until you find out that... PMOS seem to be leaky in this lot!! Or - HSR resistor is way out of spec at the edge of the wafer!! Or - oops, I didn't account for process variation, so although this wafer is in spec, my part falls apart due to... You don't want to have to tell your boss that one.. ;-)


I know it sounds terribly long, and all you want to do is crank out products, but please try to follow a clean and standardized flow.. You will do many, many chips in your lifetime, and I've seen easy screwups cause months or years of rework that could have been avoided if a designer had simply taken his time, and done it right.

Good luck! The simple fact that you ask these questions means you're on the right track - there's no better thing than a strong foundation!!
 

electronrancher.........u are also not bad....even better...i can tell u ahve more experience than me

Added after 9 minutes:

No i think u r the manager on IC's design dept...able to see thing in the big picture and know every engineer position function plus what to expect....

My respect to u...hope to be like u

Thanks for the knowledge
 

Electronrancher...u've put in really simple words a generic flow i was trying to figure out...thank you very much
 

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