Following input voltage with JFET

[shredder929]

I'm trying to make a peak detector for small voltages (<500mV). Normally a capacitor would hold the peak, and a diode prevents charge from flowing back when the voltage swings lower than the held peak. I can't use a diode to control current to the capacitor because it's such a small voltage, the lowest expected peak being 40mV.

So I'm playing around with different ways of preventing the charge from flowing back to the op-amp that sources the signal. What I thought I'd do is use a JFET instead. When the gate is 0V, the source follows the drain with only ~5mV difference. When I pull Vgs low, it gets pinched off.

It's generally working as expected but there's some weirdness that goes on. It's present in the ideal model and gets worse when I use models of real parts. I've attached screenshots of the simple setup I'm simulating, a graph of the output with an ideal JFET, and with a real JFET (the 2N3819). What is going on with those dips? Why isn't it holding it straight like I'd expect? I've been trying to find a pattern but it doesn't seem to occur with any rhyme or reason.

Any help is appreciated, thank you!

https://imgur.com/a/Qs90TjS

 

[KlausST]

Hi,

There are peak detectors, peak detector circuits, active rectifiers...
Did you do an internet search?

Btw: Any timing information is also important to get useful feedback.
Some expect a peak detector for Gigahertz signal, others want peak detection of mains voltage.

A diode solution with negative (buas) voltage could also work.

Klaus

 

[shredder929]

I did do a search, I found an app note from Analog Devices that I'm going to try out. Input signal will be from 100Hz to 10kHz. I've got the active rectification done, I just need to prevent the capacitor from discharging when the voltage goes back down.

Regardless, I'm still curious what's going on with this JFET. I thought they just pass through at Vgs=0V and block when Vgs goes lower but there seems to be some other effect at play here.

 

[FvM]

Gate voltage isn't negative enough to keep the JFET in cut-off. Negative input voltage can turn it on.

 

[BradtheRad]

I made a project with a 3819 jfet. It's depletion mode. To turn it off requires a negative voltage at the gate. A couple of volts below 0v ground. No current flows out of the gate.



Notice 0v ground is the join between the power supplies.

To turn on the gate apply 0 or more volts above ground. Current then flows into the gate, which must be limited to avoid ruining the device.