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Folding Interpolation ADC SNR problem

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chemaphy

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Hi Everyone,

I have just designed a 8-bit folding interpolation ADC. When I simulate my ADC, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the ADC. Can anyone who has experience with folding interpolation ADC let me know which part in the ADC contribute such a high noise?

Thanks,
chemaphy
 

maxwellequ

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A few questions:

Are you making a transient simulation with noise ?
How many fft points have you used ?
Do you get distortion ? To what level ?

Regards
 

chemaphy

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Thanks to your reply maxwellequ. The transient simulation that I have used is a typical one. It should not have any noise component in it. The simulator that I used was hspiceD. The noise floor in the simulation result was -40dB, and the distortion level is -30dB. Is there anything I can do to lower the distortion and noise level? Thank you very much for your time maxwellequ!
 

maxwellequ

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HSPICED ! Don't you mean HSPICE ?

Can you attach the FFT result figure ?

Anyway, the only reason to have distortion is a design error in one of the blocks. For example:
- Do you use S/H ? If yes, have you simulated it standalone (with its load, of course) ? Do you see any relevant distortion there ?
- Are you sure that the folding stages are settling fast enough ?
- Are there any DC deviations in the zero crossings of the folding stages ?
- Are your comparators fast enough ?


In what concerns the high noise floor, how many points have you used in the FFT ? If the number of points is low, then this may explain the high noise floor.

Regards
 

neoflash

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if u are familiar with cascaded folding, maybe you can help me explain it.

Added after 37 seconds:

By the way, you can not get noise from transient simulation in hspice. Never.
 

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