Folded cascode opamp biasing and stability

[viperpaki007]

Hi,

I have designed a folded cascode two stage opamp on 130nm process. The opamp works fine. Figure below shows the gain and phase response of opamp. It has 45 degree phase margin. Now the next step is to design circuit which generated the bias voltages for opamp. For initial case i used a resistive voltage divider to generate bias voltages (as shown in figure below). However, as soon as i generate bias voltages using a resistive voltage divider, my stabilty response becomes really poor. See figure below. I have no clue why that happens. Can somebody explain the degradation of stability response by adding resistive divider for biasing. What should be the right way to bias the opamp.

regards

 

[SIDDHARTHA HAZRA]

You can use the biasing circuit in the pic or the low voltage counter part of the same (Refer to Design of analog CMOS integrated circuit by B.Z.Razavi).

Hope this will help ...

 

[viperpaki007]

Hi Siddhartha,

Thanks for the help. I made you mentioned biasing circuit for the required biasing voltages and connected with my folded cascode opamp. However, the main problem remains the same. As soon as i connect biasing circuit with the bias voltage points of folded cascode opamp. Circuit stops working. Stability response show huge drop in gain and unity gain frequency. See screenshots attached for folded cascode opamp with and with out the biasing circuit.

Transient simulations of the circuit without biasing circuit show some glitches in the start time. This made me think that there may be something happening to the circuit at time t=0. To test this, i used a pulse supply voltage for opamp, which turned on after 10ns. After doing this i am able to run the transient analysis and the circuit seems to work after 10ns. Do you have any idea what is happening to the circuit at time t=0. and how should i plot the stability curves in this case.


Opamp stability response after adding bias circuit


Opamp stability response before adding bias circuit


Opamp transient reponse with bias network when a pulse supply voltage is given. Without pulse, transient simulations don't converge


Opamp transient response without bias network.


Opamp with bias network

 

[SIDDHARTHA HAZRA]

Hi viper,

As soon as i connect biasing circuit with the bias voltage points of folded cascode opamp. Circuit stops working. Stability response show huge drop in gain and unity gain frequency.
Opamp with bias network

I looked at your circuit ....but it would be great if you can provide the top level configuration (i.e whether the op-amp is used as a unity gain buffer or any other configuration) and the target current numbers in each branch, that way I can help in sizing the MOSFETs.

The I/P pair is rail-2-rail, that means either N-diff or P-diff or both should be operating. The regions shown in the schematic shows MN10 & 11 @ region=0 (cut-off) and MP14 @ region=2 (saturation) while MP15 @ region=0 (cut-off). May be so you are not getting gain. Check you biasing, may be gain will improve. Typically your circuit should give you 100-120 dB of gain.

For the biasing point of view, why are you using vbiaspa for both N & P cascode MOSFETs ?? wouldn't it be better to have a similar PMOS bias generating arm from where you can provide bias to the PMOS cascode MOS (MP16/17).

One more thing, you can choose any current distribution but take care that the MOS size ratios are in accordance to the sizing principle of current mirrors. In that way you can generate appropriate bias for that current.
Eg: Say MN15 & 14 has current I then MN10 & 11 will have I/2 each.
Same is for MP9=I and MP14 &15 = I/2 each.
Now in the main cascode arm MP11&12 should have at least I current as they are supplying current to the N-diff & to their lower circuits. So if MN10 is taking away I/2 MP17 should have I/2 and same is with MP16.
MN12&13 should alos have I/2 each. Now MP14&15 are pumping in I/2. So MN16&17 should again have I current each.
So sizing has to be accordingly done ....

Hope this will help ....

 

[viperpaki007]

Hi Siddhartha,

Thank you for the help so far. You can find my answers in RED below:


I looked at your circuit ....but it would be great if you can provide the top level configuration (i.e whether the op-amp is used as a unity gain buffer or any other configuration) and the target current numbers in each branch, that way I can help in sizing the MOSFETs.

The circuit is working in unity gain configuration. Overall current consumption requirements are less than 4.5mA. Stage one ( including transistors MN10, MN11, MP14 and MP15) was designed for 500uA current. while Stage 2 (including transistor Mp13) was designed for 1mA current. I did not go for high current is stage two because high unity gain bandwidth was not a requirement.



The I/P pair is rail-2-rail, that means either N-diff or P-diff or both should be operating. The regions shown in the schematic shows MN10 & 11 @ region=0 (cut-off) and MP14 @ region=2 (saturation) while MP15 @ region=0 (cut-off). May be so you are not getting gain. Check you biasing, may be gain will improve. Typically your circuit should give you 100-120 dB of gain.

I am attaching dc-simulation results for both cases when bias circuit is attached and when it is not. The dc-simulations results are quite weird for me(See Fig 4 and 5). As soon as i connect bias circuit, MN10 and MN11 go into cuttoff state while the voltage drop across MN14 becomes 4.0V which is more than supply voltage of 3.7V. It is so strange that i haven't even connected anything with MN10 and MN11 but they still go in cuttoff region.


For the biasing point of view, why are you using vbiaspa for both N & P cascode MOSFETs ?? wouldn't it be better to have a similar PMOS bias generating arm from where you can provide bias to the PMOS cascode MOS (MP16/17).

Because, the bias voltages required at vbiasp and vbiasnb are same (2V).

One more thing, you can choose any current distribution but take care that the MOS size ratios are in accordance to the sizing principle of current mirrors. In that way you can generate appropriate bias for that current.
Eg: Say MN15 & 14 has current I then MN10 & 11 will have I/2 each.
Same is for MP9=I and MP14 &15 = I/2 each.
Now in the main cascode arm MP11&12 should have at least I current as they are supplying current to the N-diff & to their lower circuits. So if MN10 is taking away I/2 MP17 should have I/2 and same is with MP16.
MN12&13 should alos have I/2 each. Now MP14&15 are pumping in I/2. So MN16&17 should again have I current each.
So sizing has to be accordingly done ....

Yes..i agree and that'w why sizing was done by considering the currents in MP9,MP12,MP11,MN14,MN17 and MN18 as I=1mA, while the currents through MN10, MN11, MP14 and MP15 were chosen to be I/2=500uA. See the dc simulations results for the case when the bias circuit is not attched. Figure 2 and 3. Overdrive voltage of each transistor was set at 0.5V.

Looking forward for your comments..


Figure 1: Opamp in unity gain configuration



Figure 2: Opamp dc simulation results without bias network attached



Figure 3: Opamp dc simulation results without bias network attached (close view)


Figure 4: Opamp dc simulation response with bias network attached


Figure 5: Opamp dc simulation response with bias network attached (close view)

 

[SIDDHARTHA HAZRA]

Hi viper,

I have a strange observation in the dc results printed beside the MOSFETS.
In your dc results without biasing circuit (Fig 2):
MP14 & MP15 (8uA current each) are in cutoff and MN10 & MN11 are in saturation (500uA current each). MN14 is taking 1mA, which it should be but MP9 is also taking 1mA now how is that possible. Again MN12/13 = 450uA then who is giving current to MN16/17 (1mA). Similar thing is happening with the biasing ckt as well.

I have a suggestion, can you check the dc operating points with the external loop open. Apply a dc common mode (no ac, no sine nothing) such that both PMOS and NMOS are turned ON (say around VDD/2) to both the pos and neg input pins. This will ensure full current is being drawn and all MOSFETs are operating. And instead of using R6 above MN0 can you use an ideal dc current source of 1mA or 500uA (size accordingly) as in general you will get a current from a current reference .... if not then just for testing purpose.

Repeat this experiment with dc common mode at 200mV and VDD-200mV.

 

[viperpaki007]

Hi Siddhartha,

Thank you for the suggestions. The dc-simulation results were strange for me as well.. As you said...how can it be possible that MP14/MP15 carry 8uA current and MP9 carry 1.12mA current. Where does the current go?. By the way these dc simulations were already done with external loop open by applying input common mode voltage of Vdd/2. However, it is difficult to make sure that both NMOS and PMOS active pairs are ON for a certain input common mode voltage range. This is because, for lower values of input Vcm, MN10/MN11 will be cuttoff while for higher input Vcm, MP14/MP15 will be cutt-off.

I solved the above problem accidentally by reducing the W/L ratios of MN10/MN11 and MP14/MP15. Previously all these tranistor W/L ratios were calculated based on 500uA current and Vod of 0.5V. This gave a certain W/L ratio. However, i wanted to increase the dc-gain and unity gain frequency. Therefore, i increased gm of MN10/MN11 and MP14/MP15 by increasing their widths. This increased the gm but the circuit, because of some weird reason, became unstable. I reduced the widths of MN10/MN11 and MP14/MP15 back to the calculated values and the circuit started working again...

- - - Updated - - -

One more connection error which i had done in my circuit was that i connected bulk terminal of MP14/MP15 with their drains rather than source. This caused abnormal dc-simulation results.