Folded Cascode opamp bias circuit

[analog_fever]

bias circuit for folded cascode

I am trying the folded cascode opmap design for the first time, and am wondering how to design the bias ckt. Attached is the ckt I have (Johns, Martin). I do not have Q12 and Q13 in place yet. I know the book provides a bias ckt, but I am looking to come up with something simpler, and am actually trying to learn how we design a simple bias ckt.

I came upto the point at which I know the currents needed thru each transistor to match my specs. The main problem is with the bias vtgs VB1 and VB2, and how to keep Q3 and Q4 in saturation. I have a 10uA current source for Ibias1. I generate Ibias2 by mirroring from Ibias1.

What determines the source voltage of Q5/Q6(or the drain vtg of Q3/Q4)?

Any guidance/insight from experienced designers is really appreciated.

 

[haff99]

folded cascode biasing

It doesn't matter if you keep Q3 and Q4 in saturation because you aren't getting any gain from those devices. however depending on how you bias VB1 you are basically clamping that drain of Q3 and Q4 to VT+excess voltage above VB1. So they will stay in saturation if you bias VB1 correctly. It matters if you keep Q5,6,7,8,9,10 in saturation otherwise your output voltage will decrease killing your gain.

 

[analog_fever]

opamp bias

Hey...thanks, was able to get all transistors in saturation using VB1 and VB2.