Folded Cascode gain equation not holding true

[crystalbrite]

Hello,

To summarise, I'm currently designing a folded cascode amplifier and the following gain equation doesn't hold true for larger ICMR (input common mode range) values and I can't figure out why.
All devices are in saturation.
Gain = gm2/((gds8*gds10/gm8)+(gds6*(gds4+gds2)/gm6))

Design attached.


I'm trying to increase the input common mode range while maintaining gain.
I've designed the overdrive on the devices to be ~150mV.
I'm using the following equation to calculate gain using the extracted operating values of gm and gds:
Gain = gm2/((gds8*gds10/gm8)+(gds6*(gds4+gds2)/gm6))

I'm using this equation to try and optimise the gain.
This equation holds true for the ICMR<3V but doesn't match the ac analysis gain for ICMR>3V.

Below shows a plot of the opamp gain as the ICMR voltage is swept from 0.6V - 4.9V.
VDD = 5.5V
VSS = 0V

The gain from the ac analysis and the gain calculated using the above equation with gm and gds values extracted using a .op analysis are plotted.

It can be seen that the gain equation matches the ac analysis very well below 3V but above 3V the gain from the ac analysis starts drops off.
I've also run a transient analysis with a small ac input signal and it matches the ac analysis.

I've also checked the operating regions of all transistors and all transistors are in saturation for ICMR = 4.9V with some headroom to spare.

Does anyone know why the gain equation doesn't hold true for the higher ICMR values?
Gain = gm2/((gds8*gds10/gm8)+(gds6*(gds4+gds2)/gm6))

Thanks in advance!

 

[dick_freebird]

You claim that all transistors are in saturation but this
can't be true across the full common mode range for
the input diff pair. Either it, or its loads, must give way
at some point.

Your bias network is simple mirrors with probably poor
lambda / current setting vs input CM on the diff pair
tail. Yet the folded-cascode sections have PMOS cascode
mirrors which should not vary much. Perhaps it is this
discrepancy, Isource vs Isink, that is pulling things apart.

I don't know about your equation, 30+ years of IC design
has failed to make me so sophisticated. But I'd bet you'll
find your answer in simpler things.

Rather than looking at whether the devices are in saturation
"by the book", how about you look at Rout / gDS, and gm,
all along the line, and see whose gm*Rout is taking the
dive consistent with the gain curve? Basic debugging, that.

 

[crystalbrite]

You claim that all transistors are in saturation but this
can't be true across the full common mode range for
the input diff pair. Either it, or its loads, must give way
at some point.

Your bias network is simple mirrors with probably poor
lambda / current setting vs input CM on the diff pair
tail. Yet the folded-cascode sections have PMOS cascode
mirrors which should not vary much. Perhaps it is this
discrepancy, Isource vs Isink, that is pulling things apart.

I don't know about your equation, 30+ years of IC design
has failed to make me so sophisticated. But I'd bet you'll
find your answer in simpler things.

Rather than looking at whether the devices are in saturation
"by the book", how about you look at Rout / gDS, and gm,
all along the line, and see whose gm*Rout is taking the
dive consistent with the gain curve? Basic debugging, that.

Hi dick_freebird,

Yes, the transistors start to come out of saturation at ~0.3/5.2V. I am only sweeping here from 0.6-4.9V where they all stay in saturation.

You say to start looking at gm and rout/gds along the line but that is what I am doing when I calculate the gain.
That's the reason I started looking at the following equation as I wanted to figure out why my gain was dropping so much.
I extract these values across the line and they tell me everything is ok.
They don't match up with with the ac analysis.

I've checked the operating conditions of all the transistors and everything seems to be ok.
I've checked the trend in gm and gds of all devices across the range and everything seems to be ok.
These are normally the two things to look at so I'm not sure where to start looking next.

The gain equation is standard for a folded cascode opamp.
Gain = gm2/((gds8*gds10/gm8)+(gds6*(gds4+gds2)/gm6))

 

[geo24]

which book are you based on, op ? Razavi ?

 

[crystalbrite]

which book are you based on, op ? Razavi ?

Yes Razavi, Sec 9.2, One-Stage Op Amps
He includes the gmb on the cascode devices in the equaiton. All this will do is increase the calculated gain though:
Gain = gm2/((gds8*gds10/(gm8+gmb8))+(gds6*(gds4+gds2)/(gm6+gmb6)))


The equation is also in the following paper, equation (8):
'Design procedures for a fully differential folded-cascode CMOS operational amplifier'
http://cc.ee.ntu.edu.tw/~ecl/Courses/101AIC/p1.pdf

 

[dick_freebird]

Here's a question - at what frequency is the AC analysis run?
High enough that maybe your problem is not a DC gain, but
a bandwidth-vs-CM falloff? Such as might come from your
compensation network changing its dominant pole or its
compensating-zero position (I see only a shunt-C compensation,
as a MOSFET, whose Cgg and Rs(eff) (i.e. the channel
resistance, to under the gate) will swing a lot with output
common mode position).

If you ran the AC analysis at freq=0.01, do your DC and AC
analysis curves begin to look more alike?

 

[crystalbrite]

Here's a question - at what frequency is the AC analysis run?
High enough that maybe your problem is not a DC gain, but
a bandwidth-vs-CM falloff? Such as might come from your
compensation network changing its dominant pole or its
compensating-zero position (I see only a shunt-C compensation,
as a MOSFET, whose Cgg and Rs(eff) (i.e. the channel
resistance, to under the gate) will swing a lot with output
common mode position).

If you ran the AC analysis at freq=0.01, do your DC and AC
analysis curves begin to look more alike?

Not shown in the schematic but I also have an external 10pF load capacitor. The compensation cap is about 1pF.

I think my common mode rejection ratio (CMRR) is dominating the gain.
Would this make sense?

If I do a DC sweep of the input common mode voltage and plot the offset, offset=vout-vin
And the do the following calculation:
Common mode gain = 20*LOG10(1/(dy/dx(offset))
This gain matches exactly the ac analysis gain from my first post.

I think the following equation only takes into account the gain of the circuit and not the limited CMRR of the circuit which is dominating:
Gain = gm2/((gds8*gds10/gm8)+(gds6*(gds4+gds2)/gm6))

Does what I'm saying potentially make sense?

I'm going to try adding another cascode transistor to the n side of the output in hopes that it will improve my systematic offset and thus CMRR and Gain.