folded cascode design ..........biasing.........

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ASHUTOSH RANE

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hello guys
i am fresher in analog design
i am designing a folded cascode amplifier (ref:- b razavi+ ken martin )
but the problem with my circuit is that i am not getting same values of Vds Vgs Id in cascode branches .........also transistors( mos ) M3 and M7 are not going saturation region ........ can anybody suggest me to improve on it ............
i too have lots of doubts about biasing the circuits like
how to bias transistors M3,M2 and M9,M7??..((..... i mean actual circuitary for that ........))

can u please suggest me some books or papers for reference ...please ..........!!!




for fig check attachment ( cadence 180 umc)
 

it seems the amplifier is in open loop, how about output voltage, which would effect cascode MOS. In my view, the biasing of cascode MOS decide common source MOS status (Linear or Saturate), while output voltage effect the casode stage.
 

Hi
You don't get equal output voltages because one of two reasons (maybe both of them):
- transistor's dimension mismatching
- absence of CMFB circuit (for high gain fully-differential amplifier it's presence is obligatory ). If you don't want build it, you can start with single-ended version of your amplifier.

Also i think you should change gate biasing voltages for PMOS ( 88 mV for cascode transistor is unacceptable). Try to increase width of PMOS or maybe increase VCC, also you can use another biasing circuit.

Regards.
 

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