foldback current limiter for LDO (attached but need explanation)

[!! the phoenix law !!]

Hi
Attached is a foldback current limiter circuit
Can some one explain please how to choose W/L for each transistor and the values of R1 and R2 ?
Thanks

View attachment CurrentLimiterLDO_3.pdfView attachment CurrentLimiterLDO_3.pdf

 

[dgnani]

Hi phoenix,

do you want to implement this in a specific technology or the calculation with SPICE level=1 would be enough?
I assume you are talking about implementing the current limiting circuitry not the whole LDO, right?

 

[!! the phoenix law !!]

Hi dgnani
I have already implemented and tested the LDO and now I just need to implement its current protection circuit
I am using tsmc13rf which is a 0.13um tech, I am doing simulations with cadence virtuoso

 

[!! the phoenix law !!]

I have another question
Actually, I am designing a power harvesting circuit where a RF signal at the receiving antenna terminals is rectified and applied to my LDO to be regulated, the problem here is that output voltage across the antenna terminals might increase in case distance between Tx and Rx decreased beyond the design limit
So, I sould protect my circuit against supply voltage increase !
I am not sure if this were similar to the over current protection but this is the only solution i was able to think about, I assumed that supply voltage increase will result in a current increase perhaps due to some Tr break down
Is this true ? If not then what is the right solution ?

 

[dgnani]

Hi phoenix

shouldn't the LDO already do just that!? ie. regulate the output voltage against input supply voltage variations?

 

[!! the phoenix law !!]

Yes but within limits (According to my results 2v:8v)
However, If the supply voltage exceeds 8v I think that the circuit connected to the LDO output should be protected, I am not sure, what do you think ?

 

[dgnani]

I see but... what kind of devices are you using to handle 8V? won't your pass gate suffer (explode?) with, say, 6V across it? (not sure what you regulated voltage will be...

do you have zener diodes in the process? that would an easy way out...

if that's not an option I think that shutting off the pass gate (which is what the current limiter does) it is not really what you want; I would rather clamp the excess voltage to ground (like an ESD clamp basically), since -I guess- you already have a reference voltage to define the regulated voltage you might as well use it to define a maximum input voltage and use a comparator to activate a large nfet to ground... how does that sound?

 

[!! the phoenix law !!]

I think you are right, I will consult my supervisor also to make sure
Thanks for you help