FN-PLL: reduction of fractional spur- where to add dither?

[ben-w]

about fractional-N PLL

I'm designing a FN-PLL, MASH1-1-1 modulator is used. But the simulated output spur is very large. Dithering maybe a simple way to reduce the fractional spur, but I don't know where to add the dither, can anyone help me?
Thanks!
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[mengcy]

about fractional-N PLL

the picture you presented is not a MASH1-1-1 scheme.

you should add dither before the delta-sigma modulation.And the dither must be much smaller than K.

 

[knights]

Re: about fractional-N PLL

why you think it is not a MASH1-1-1 scheme.?
In many papers, I find the same architecture that used in fractinal PLL.

the picture you presented is not a MASH1-1-1 scheme.

you should add dither before the delta-sigma modulation.And the dither must be much smaller than K.

 

[ben-w]

Re: about fractional-N PLL

Hi mengcy：
You are right, the post structure is MASH1-1-1-1.
Should I add dither at the input of the first accumulator?
In my design K is 24bit, the lowest bit is a pseudo-random signal, but the simulated result shows the fractional spur is about -30dB, the spur is still very large.how to slove the problem?
Thanks !

 

[mengcy]

Pls tell the way you simulated. Is the spur you got from the closed loop pll simulation or the sdm itself?
and what is your fractional number? The spur depends on your input fractional number!

 

[ben-w]

Re: FN-PLL: reduction of fractional spur- where to add dithe

The spur is from the close loop simulation. All the blocks of pll are modeled in Veriloga.
When the fractional number is 0.5, the spur is about -50dB. When the fractional number is 0.25, the spur is about -30dB.
What bothering me is that there is nothing different whether the LSB of input dithering or not.
Can you tell me why?
Thanks!