[SOLVED] Fmax in quartus II- Direct form FIR filter

[Farid Shamani]

It might be a silly question, but i wonder if having a higher Fmax is an advantage regarding to timing analysis. For example is a 200 MHz Fmax better than 120 Mhz or it is proportional to other criteria.

I have implemented the VHDL codes regarding to Direct-Form FIR filter in both pipeline and sequential form. However, i know the sequential form is suffering from a long delay path related to the time taken by a multiplication, plus the time taken for summation of all TAPs ( Tcrit = Tmul + (N*Tadd)), while this time is reduced to Tcrit = Tmul + Tadd due to the pipelining.
When i synthesis both pipeline and sequential form, i have a result of 146 MHz for pipelined version while this result is 259 Mhz for sequential one !!!!

Could someone explain why it is happening.

Thanks,
Farid

 

[TrickyDicky]

Well, its also going to depend on data rate. If you have something clocked at 200 Mhz, but can only input 1 value every 4 clocks, it will have lower bandwidth than something with a clock of 100Mhz but 1 value every clock (2x the bandwidth). So you need to consider this too.

But usually with these things the higher the fmax, the shorter the worst case path is between two registers (ie. less logic). Higher is usually better for a similar design.

 

[Farid Shamani]

Thank you dear Tricky,

It made me more confident