sph3r3
Member level 1
floorplanning xilinx ise
1. Does anyone know of tutorials that show how to use ISE to floorplan the modules in an FPGA design?
2. Once I have floorplanned a design is it possible to find out the input-to-output timing of a single module? The way I have been doing this is to make a new project containing only a single module and running through synthesis + P&R but this includes pad delays which I don't want.
I don't think the documentation is very good for this.
Thanks,
sph3r3
1. Does anyone know of tutorials that show how to use ISE to floorplan the modules in an FPGA design?
2. Once I have floorplanned a design is it possible to find out the input-to-output timing of a single module? The way I have been doing this is to make a new project containing only a single module and running through synthesis + P&R but this includes pad delays which I don't want.
I don't think the documentation is very good for this.
Thanks,
sph3r3
