mjelahi
Newbie level 5
floorplanning soc
When you load a design into SoC Encounter, you get pink module guides and green hard blocks on the side of the core area of the chip. My understanding is that if you go for flat implementation, you only place the hard blocks inside the core area. The module guides are left untouched outside the core area. Is that true?
And if you are going for hierarchical implementation, then the pink module guides are placed inside the core area and converted into partitions or fences. This way no standard cell goes out or comes into the defined module area when performing standard cell placement.
Can somebody please verify if my understanding is correct?
When you load a design into SoC Encounter, you get pink module guides and green hard blocks on the side of the core area of the chip. My understanding is that if you go for flat implementation, you only place the hard blocks inside the core area. The module guides are left untouched outside the core area. Is that true?
And if you are going for hierarchical implementation, then the pink module guides are placed inside the core area and converted into partitions or fences. This way no standard cell goes out or comes into the defined module area when performing standard cell placement.
Can somebody please verify if my understanding is correct?
