Floating Point Representation in Hardware

[SyedSJ]

Hello all ...

Im working on the project 'FPGA Designing of 802.11a Transmitter' for the past 4 months as my first HDL Project n im having a difficulty in deciding the format suitable for representing the floating point values of I n Q in the mapper module.

The mapper maps the bits as per the constellation table n the values after multiplication with the normalization factor is converted into floating point values e.g 0.707,0.316 ...

Kindly suggest the proper format for representing the floating data at the hardware level ... im working wid the Half-Precision Format of Representing Floating Point but not sure about that .

Waiting in anticipation .

Regards
Syed Shaheer Javaid

 

[indranilh]

you can convert this to as a fixed point number by multiplying it with the no of 2's power.i mean to say multiply .707 with 1024(2^10).

 

[Nikolai]

U can use wat is called as Q-7 fixed point format. Most DSP processors use it for performing operations on fractions

U'll the attached PDF useful

 

[SyedSJ]

Thanks for the prompt response ...

I will look into both of these possiblities ... but why we cannot represent floating point values by Double Precision Floating Point Representation (64_Bit), Single Precision Floating Point Representation (32_Bit) or Half Precision Floating Point Representation (16_Bit) ?

I will be grateful if u answer the query ...

Thanks once again

Regards
Syed Shaheer Javaid

 

[echo47]

Most FPGA designers use fixed-point techniques because today's FPGA's don't have any built-in floating point logic. Trying to implement floating point arithmetic in FPGA logic fabric usually results in a big slow design. Fixed-point arithmetic is much smaller and faster.

 

[SyedSJ]

Thank u all for the support ... uploading a presentation that descibes that in detail ...