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floating point adder : need help for solving error

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mo.khairy.mo

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Hi all,
i'm trying to design a floating point adder using advantage pro and i simulating it using modelsim
this my code

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY fp_adder IS
-- Declarations
port(a,b: in  std_logic_vector(31 downto 0);
	   c: out std_logic_vector(31 downto 0)
	);
END fp_adder ;

-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign 
signal sa,sb,sc: std_logic;
--declaration of exponent
signal ea,eb,ec: unsigned(7 downto 0);
--declaration of mantissa
signal ma,mb,mc: unsigned(22 downto 0);
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
ea <= unsigned(a(30 downto 23));
eb <= unsigned(b(30 downto 23));
--assignement of mantissa signals
ma <= unsigned(a(22 downto 0));
mb <= unsigned(b(22 downto 0));
------------------------------------------------------------------------------------------------------
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
begin
	if(ea > eb)then loop
	eb <= eb+1;
	mb <= '0'& mb(7 downto 1);
	exit when ea=eb;
	end loop;
	elsif(eb > ea) then loop
	ea <= ea+1;
	ma <= '0'& ma(7 downto 1);
	exit when ea=eb;
	end loop;
	else
	mc<= ma+mb;
	ec<= ea;
	sc<=sa xor sb;
	end if;
end process;
	c(22 downto  0) <= std_logic_vector(mc);
	c(30 downto 23) <= std_logic_vector(ec);
	c(31)		    <= sc;
END adder;
and i found a problem which i couldn't recognize it
there is no error in compiling the code
but at simulation the o/p is UUUUUUUUUUUUUUUUUUUU

and there is some warnings at modelsim command window
this is the error massage
Code:
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder

can anyone kindly help me to solve the error
 

lmtg

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I guess it could be because you didn't assign the output in the first part of the if. You only assigned it for the else condition..
 

mo.khairy.mo

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thanks alot but it still the same error
i think the error at the signal assignment because there is no change in any signal neither mantissa nor exponent
 

lmtg

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Yes, you didn't assign the signal mc or ec in the if only in the else. Hence, a problem occured in the output. So try assigning mc and me in the if and see what happens.
 

mo.khairy.mo

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this the code after editing it


Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY fp_adder IS
-- Declarations
port(a,b: in  std_logic_vector(31 downto 0);
	   c: out std_logic_vector(31 downto 0)
	);
END fp_adder ;

-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign 
signal sa,sb,sc: std_logic;
--declaration of exponent
signal tea,teb: std_logic_vector(7 downto 0);
signal ea,eb,ec: unsigned(7 downto 0);
--declaration of mantissa
signal tma,tmb: std_logic_vector(22 downto 0);
signal ma,mb,mc: unsigned(22 downto 0);
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
tea <= std_logic_vector(a(30 downto 23));
teb <= std_logic_vector(b(30 downto 23));
ea <= unsigned(tea);
eb <= unsigned(teb);
--assignement of mantissa signals
tma <= std_logic_vector(a(22 downto 0));
tmb <= std_logic_vector(b(22 downto 0));
ma <= unsigned(tma);
mb <= unsigned(tmb);
------------------------------------------------------------------------------------------------------
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
begin
	if(ea > eb)then loop
	eb <= eb+1;
	mb <= '0'& mb(7 downto 1);
	exit when ea=eb;
	end loop;
	mc <= ma+mb;
	ec <= ea;
	sc <= sa xor sb;
	elsif(eb > ea) then loop
	ea <= ea+1;
	ma <= '0'& ma(7 downto 1);
	exit when ea=eb;
	end loop;
	mc <= unsigned(ma+mb);
	ec <= unsigned(ea);
	sc<= sa xor sb;
	else
	mc <= unsigned(ma+mb);
	ec <= unsigned(ea);
	sc<= sa xor sb;
	end if;
end process;
	c(22 downto  0) <= std_logic_vector(mc);
	c(30 downto 23) <= std_logic_vector(ec);
	c(31)		    <= sc;
END adder;

and still the same error

i'll attach the code to you
can you simulate it and see what's the error
[/code]
 

FvM

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Apart from the simulation error, it's no synthesizable design. It also has VHDL expression errors, e.g. nonmatching size
mb <= '0'& mb(7 downto 1);
 

mo.khairy.mo

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could you explain to me why it's not synthesizable design?
sorry but i'm new at vhdl and the floating point its a part of my graduation project "design of graphics card processor" can you suggest to me any method to design the floating point adder & multiplier also i need to learn my errors at this code to not repeat the same errors again
 

mo.khairy.mo

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this the new vhdl code after add a default value for all internal
signals

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY fp_adder IS
-- Declarations
port(a,b: in  std_logic_vector(31 downto 0);
     c: out std_logic_vector(31 downto 0)
  );
END fp_adder ;

-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign 
signal sa,sb,sc: std_logic:= '0';
--declaration of exponent
signal tea,teb: std_logic_vector(7 downto 0):= (others=>'0');
signal ea,eb,ec: unsigned(7 downto 0):= (others=>'0');
--declaration of mantissa
signal tma,tmb: std_logic_vector(22 downto 0):= (others=>'0');
signal ma,mb,mc: unsigned(22 downto 0):= (others=>'0');
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
tea <= std_logic_vector(a(30 downto 23));
teb <= std_logic_vector(b(30 downto 23));
ea <= unsigned(tea);
eb <= unsigned(teb);
--assignement of mantissa signals
tma <= std_logic_vector(a(22 downto 0));
tmb <= std_logic_vector(b(22 downto 0));
ma <= unsigned(tma);
mb <= unsigned(tmb);
------------------------------------------------------------------------------------------------------
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
begin
  if(ea > eb)then loop
  eb <= eb+1;
  mb <= '0'& mb(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  elsif(eb > ea) then loop
  ea <= ea+1;
  ma <= '0'& ma(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  else
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  end if;
end process;
  c(22 downto  0) <= std_logic_vector(mc);
  c(30 downto 23) <= std_logic_vector(ec);
  c(31)        <= sc;
END adder;

i try to test my design by put
a =.25 "00000000101000000000000000000000"
b =.25 "00000000101000000000000000000000"
so
sa=0
sb=0
sc=0
tea=000000001
teb=000000001
ea=0000000X --i can't understand why?
eb=0000000X --i can't understand why?
tma=01000000000000000000000
tmb=01000000000000000000000
ma=0X000000000000000000000 --i can't understand why?
mb=0X000000000000000000000 --i can't understand why?
mc=XXXXXXXXXXXXXXXXXXXXXXX but i expect to be ="10000000000000000000000"

plz can you explain why there's unknown bits?
 

FvM

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When trying to synthesize the design as is with a VHDL compiler, you get an "infinite loop" error on the first loop. This is because the compiler can't easily detect the maximum number of iterations. Apparently, your simulator isn't disturbed by this problem. You can modify the code by adding an explicite loop range (e.g. 1 to 255), but you run into a more fundamental restriction.

You should consider, that VHDL is a hardware desciption language and an iteration doesn't mean to repeat a certain block, but requests parallel instances of the included code.

So if you allow up to 255 iterations (incrementing an 8 bit unsigned), you build 255 shift register instances.

You can possibly get correct results in a VHDL simulator, that is only interpreting the code, but it's effectively unsynthesizable.

The X in your simulation is due to additional VHDL design errors. A signal can't be assigned multiple times in a loop, you have to use a variable instead.
This is the case with ea, eb, ma, mb.

Seriously, no synthesizable float arithmetic core works without a clock and pipelined execution over a number of clock cycles.
 
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