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[SOLVED] Floating Pins after Power Planning

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Mariammm

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Hi,

I have a problem regarding the power planning step.

When I check the connectivity of the net after the power planning stage, I find that the design is open and all nets are floating.
So, can anyone tell me what is missing in the power planning stage and what causes this error?
I attached below a copy of the command verify_pg_nets execution results.

Thanks,


icc_shell> verify_pg_nets
Create error cell cv32e40p_core.err ...
Checking [VSS]:
There are no floating shapes
ERROR: There are 17855 floating pins
Checking [VDD]:
There are no floating shapes
ERROR: There are 17855 floating pins
Checked 2 nets, 2 have Errors
Update error cell ...
1
 

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