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Floating Nodes in LTSPICE

Yukta2007

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WhatsApp Image 2020-09-15 at 6.23.57 PM.jpegPlease help me in correcting these mistakes.
 

FvM

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The question can be surely answered if you show a circuit diagram.
 

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Not yet obvious, P1 to P4 seem correctly connected. Can you show the net list?
 

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Not the same circuit that produced the error messages in post #1. Now P3 and P4 have unconnected substrate pin. Check the schematic design.
 

Yukta2007

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Not the same circuit that produced the error messages in post #1. Now P3 and P4 have unconnected substrate pin. Check the schematic design.
Sorry. I had uploaded the wrong file earlier.
 

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FvM

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Right, P1 and P2 have unconnected substrate node, not P3 and P4 as l wrote erroneously.
 

Yukta2007

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So how can that be corrected?
 

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Delete P1 and P2, reinsert PMOS4 symbols and connect source and substrate correctly.
 

Yukta2007

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Is it not connected properly now? What all changes has to be made?
 

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Seriously I don't understand how you managed to get unconnected substrate (bulk) of P1 and P2. By using the PMOS instead of the PMOS4 symbol, substrate is normally connected to source node. As you see in the net list, it's not the case in your circuit. Thus I suggested to place the repective symbols a new.
 

Yukta2007

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Since we are using 65nm technology, we have downloaded the model card from http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm, We have chosen pmos4 and nmos4 from components list only but changed the names to PMOS and NMOS so that the model card can be included here.
 

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O.k., as you pointed out, the problem is brought up by using the 3-pin symbol with this model for P1 and P2. Why don't you simply replace it with PMOS4?
 

Yukta2007

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Now we are getting this error. Actually we're trying to generate efficiency report for transistor level XOR gate because we're in need of power dissipated by the whole circuit.
 

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FvM

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Yukta2007

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Can we use .step and .meas to calculate the avg power dissipated? If yes, can you please tell for how many cycles should we calculate?
 

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Why .step? 1 cycle should be sufficient for measurement. The interval start and end should not coincide with a signal edge. You can do the measurement in waveform viewer if you set the plot limits to an integer multiple of cycles. But .measure statement will do well.
 

Yukta2007

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Why .step? 1 cycle should be sufficient for measurement. The interval start and end should not coincide with a signal edge. You can do the measurement in waveform viewer if you set the plot limits to an integer multiple of cycles. But .measure statement will do well.
can you tell me If in the given circuit .meas V(out)* I(load ) will give proper power value? Or do you have any other suggestions for the formula that can be used?
[load is the name of the current source.]
 

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FvM

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V(out)*I(load) is the power consumed or supplied by the load. But I don't understand the purpose of this setup.

Looking closer to the schematic design, I see that you have drawn several non-connecting wires that end with open end. The same problem was already causing the single pin node warnings reported in previous posts.

In the detail copied from post #3, the red arrow marks an unconnected wire end. It ends at an internal graphic line of the symbol instead of the pin. If you look sharp, you can distinguish the darker blue of internal symbol graphic lines and lighter blue of connecting wires.

1600438851161.png

Even if these wires at N3, N4, P3, P4 have no intended function, I would delete it to avoid confusion.
 

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