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Floating node error while trying to simulate PSPICE model

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abbeyromy

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Hey guys i am totally stuck at this problem.

I downloaded the .subs file for LT1763- Fixed 3.3V LDO regulator and created a schematic symbol for it, then attached the model to the part, included it in schematic and was trying to simulate the basic circuit as shown in datasheet.

Now as per datasheet you need to have a capacitor between the BYPASS and SENSE terminals. If I try to do that I get a floating node error. If I try to keep Bypass as NC then I receive a DRC which stops the simulation..

Kindly help me... I have attached the datasheet..

In general if I want to try connect 2 pins of IC with a capacitor..should that be a problem?
 

keith1200rs

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Try putting a very large value resistor on the bypass pin (1G ohm will do - if not, try a little lower). It floats otherwise.

Keith.

Added after 11 minutes:

Actually scrub that idea. What connections have you used for the subcircuit? The header of the model says

* terminal definitions
* ----------------------------
*& VIN
*& VOUT
*& SENSE
*& VGND
*& BYPASS
*& SHDN

But that doesn't work. The node order is

OUT
Sense
GND
BYP
SHDN
IN

Then it works.

Keith.
 

    abbeyromy

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abbeyromy

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Hi keith,

First of all thanks a lot for replying and helping me.

Ok I tried doing 1G thing.. It does not work :(

I am trying to implement the fixed 3.3V LDO example given on the first page of datasheet..

Regarding order I will explain you how I have done

The subckt file gives the following info

* terminal definitions
* ----------------------------
*& VIN
*& VOUT
*& SENSE
*& VGND
*& BYPASS
*& SHDN

Next it defines .SUBCKT LT1763_33 1 2 3 4 5 8
So my assumption is it is saying that

NAME PIN NAME

VIN 1
VOUT 2
SENSE 3
VGND 4
BYPASS 5
SHDN 8

Now I import this to create a symbol and what I get is a box with same pin name and pin number.
The pin number is all junk and I see the datasheet and correct the pin number as per the function.. so see the below table



NET/ PIN NAME/ PIN number as per datasheet

VIN 1 8
VOUT 2 1
SENSE 3 2
VGND 4 3
BYPASS 5 4
SHDN 8 5

I am also attaching the OLB file I made from txt subckt file..

I request you to please help.
Thanks again
-Hemanshu

After this the pin number and functioning gets fixed and I only rearrange pins to get the schematics as per datasheet (on the first page)

Added after 3 minutes:

ok one more thing
I read this online about handling pin name in subckt file

Edit the pin numbers and pin types. Do not change the pin name because that is the way
the symbol relates back to the Spice model.
 

keith1200rs

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I cannot see the .OLB file you attached. I don't use Pspice any more (not since DOS) although I have Orcad so should be able to read the OLB. What would be more useful though is the output file from the failed simulation. I am not sure of the extension (.OUT?) but if you could send that, I can check against what I found worked. I can even run the netlist if you have the .CIR or .NET file.

Strictly speaking SPICE only cares about pin order on subcircuits, but other simulators may make their own modifications to that.

Keith.
 

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