Flattening in synthesis

[alam.tauqueer]

Can any one tell me What is flattening in synthesis?

Regards
Tauqueer

 

[sizzlers]

flattening is nothing but go down to the hierarchy,i.e from top level to last level.
correct me if i am wrong

thanku

 

[research235]

hello

If i understand u correctly ur talking abt flat desin before synsthesis part. since VHDL r Verilog coding is in hierarchy way and there naming at diffent stages and if we do not give as flat then there will be naming clash for the same name . so in order to over come this ,, we declare it as flat and then we get the final net list after synthesis .

may be i am wrong please let me know

 

[sam536]

Please check the below page for flatening details..



As I explained in the above page (wrto DC),

Flatening works by converting the combo logic into two level SOP(sum-of-product) form and removing intermediate terms.

How set_flatten Worsk in DC :
Product = X * W;
X = Y+Z;
when you set , set_flatten true in DC , the optimization will be ,
product = (Y+Z) * W => Y*W + Z * W;


Flatening is oftenly mistaken for removing the hierarchy and making the design flat . Ungrouping removes levels of hierarchy in a design

 

[alam.tauqueer]

So flatening is basically generate netlist by removing intermediate combo logic and optimized into SOP.
please tell if my understanding is wrong.

 

[RBB]

Sam hit it on the head. Synposys uses some confusing naming, but flattening is changing combinational logic into sum-of-products. Ungrouping removes heirarchy. Both can improve timing. Depending on the design they may reduce gate count.