Flattening Hierarchical Layout for Routing LEF

[arturoEE]

Hello,

I am using Cadence Innovus, and have designed a block that will be duplicated many times to make up my layout. I have saved this block as a *.LEF file, and instantiated it many times in my top-level project. I am curious to know if there is a way to flatten my layout or to export it such that I can route over/through my *.LEF blocks, as currently everything must be routed around them, leading to a much larger area.

For example, my blocks are routed on M1 and M2, and have a power grid on M4, M5, but M3 is empty. I cannot route through my blocks on M3 currently in my top-level design which means I'm wasting area. Is there a way to solve this issue?

Thanks so much for your assistance.

 

[ThisIsNotSam]

when creating your blocks, make sure you are not setting M3 as obstruction

 

[arturoEE]

Thanks for the hint! Obstruction was the word I was missing.

For any other beginners looking to do this using the flag [-cutObsToExposeRouting distance_in_microns] on write_lef_abstract and setting the distance to half the maximum W/L of the chip will remove the obstruction.