FLASHPRO JTAG signal integrity

[Rodney123]

Hi All,

I am attempting to program MPF300T-1FCG784I device using Libero v12.6 (Platnium) with FlashPro 4 programmer (JTAG). However I get the following error when programming.


Error: programmer '01416' : device 'MPF300(T|TS|TL|TLS)' : Executing action PROGRAM FAILED, EXIT -22, refer to FlashPro online help for details.

More information this error

To deal with this issue I have taken a closer look at my JTAG signals to see is signal integrity could be an issue.

Green: TMS
Purple: TDI
Blue: CLK
Orange: TRST

To achieve this JTAG "frame" I ran a "Scan and Check Chain" operation.

So my questions are as follows:

Do the above JTAG signals look acceptable?
I have noticed that both TMS and TDI seem to float until the CLK kicks in

Should reset be high during the transmission of the frame?
I believe the JTAG State machine to be active whilst TRST is low. am i pumping data in to a SM that is in reset.

Is their a resource that describes JTAG framing and protocol?
most of my questions stem from a weak understanding of what JTAG signals should look like (framing and protocol).

What exactly does the "scan and check chain" do?
At a guess I would say checks the programmer is connected and that it can clock data into and out of the target device/s Instruction register/s as expected.

 

[barry]

TRST is active-low, so that’s not your problem.

its hard to tell anything about your signal integrity over such a long sample, you’d need To zoom in to see anything of interest.

without seeing your setup, and based on the error messages, I suspect you’ve got a problem with cabling. Try programming at a slower clock speed and see if that helps.

 

[ads-ee]

TMS should never float that is the signal that moves a TAP controller through the FSM.

Do you have the TMS line connected to a pullup?

 

[KlausST]

Hi,

Intermediate levels could mean "floating signals" ... but it could also mean "short circuited" signals.

Please check wiring.
In doubt use a series 100 Ohms resistor and measure at both sides.

Klaus

 

[Rodney123]

TRST is active-low, so that’s not your problem.

its hard to tell anything about your signal integrity over such a long sample, you’d need To zoom in to see anything of interest.

without seeing your setup, and based on the error messages, I suspect you’ve got a problem with cabling. Try programming at a slower clock speed and see if that helps.

More detailed JTAG signals:

Green: TDO
Purple: TMS
Blue: TDI
Orange: CLK

hope this is a little more clear.

I am programming a slow as possible at this point @ 1Mhz

Set up is as follows: (apologies for unconcise schematic, there are two PCB's. one with JTAG header (PCB1) and one with FPGA (PCB2).)

Figure 1: JTAG 10 pin connector (PCB 1)

Figure 2 - 3: PCB1 to PCB2 socket with filtering

Figure 4: JTAG into FPGA (PCB2)

Finally, in a effort to ensure cabling between programmer and board was not causing the issue I put together this cable.

As far as the reset is concerned, when a reset occurs the JTAG FSM goes to TEST-LOGIC-RESET state. when reset goes high, the programmer will drive the operation through TMS. Does this sound about right?

Thanks

 

[Rodney123]

TMS should never float that is the signal that moves a TAP controller through the FSM.

Do you have the TMS line connected to a pullup?

TMS has no pull up. This is in line with the board design specified by the FPGA manufacturer however.

as a result it does tend to float.

 

[digidigi]

TMS has no pull up. This is in line with the board design specified by the FPGA manufacturer however.
View attachment 173348
as a result it does tend to float.

Hi,
Do you solve the problem?
please answer.

 

[dpaul]

@Rodney123,
Do you have another FlashPro programmer to try out ? The one which you really know has been successfully used by a colleague.
Did you try to generate the FPGA bitstream again doing a "Clean and Run All" and trying it out?