Flash Memory addressing latch up.

[sh-eda]

I hope I have posted this is in the correct forum as I believe it is a hardware problem with a device that I need help with.

I am investigating an intermittent problem that has baffled me. The specific device, 28SF040 512K x 8bit flash memory device, is manfactured by SST. Though someone may have a similar experience with other flash devices. I have contacted SST without reply.

4 devices are used in parrallel, among other things, to store the bootcode for an Analog devices DSP.

Under certain power up conditions it appears that the flash devices become latched up, and will only read from the first address location 0x00.

So trying to read a different address location I get the same result. I used a logic analyser to verify this.
I also know that it is only reading address 0x00 because I have altered the content at 0x00 using a seperate EEPROM programmer, and then read it back using the analyser.

Unfortunately the first thing the DSP does is to read address 0x03 not 0x00. It needs this information in order find the start of the boot code. So the DSP fails to boot.
My suspicion is the address is latched internally. I have checked the read/write timings cycles and they appear to be correct.

Anyway any help would be appreciated.

Thanks

 

[barry]

Under certain power up conditions

I think that might be the key. Are there certain power-up requirements for this device? e.g., monotonic supply rise, minimum/maximum power supply rise time? Are control inputs held in a known state during power up?

 

[sh-eda]

Thanks for replying.

Yes that's actually the conclusion I came to, but I wondered if anyone else had any similar problems with these devices, as I have not had
that much experience with using them.

The control pins are held high at power up via some programmable logic. This provide address decoding / mapping.

Originally the 5v rail was poor, and used to rise very slowly (30ms) and there was a slight delay around 3v (because of a loading effect in
another part of the circuit and a switch mode PSU coming up none of which I can change).

I altered the supply circuit, using a 5v regulator with an enable pin, so it only came on when the incoming supply was above the correct
level. That got the supply rise time to a much cleaner 1-2ms, and I hope has fixed it.

The device datasheets says "powerup supply to read operation" < 10ms but I found it had to be much less than that to work.
So I am still worried that the devices are still capable of getting into a latched state which I can not find a way to free. I can see that if there is a PSU glitch this still maybe a problem.

It seems like the address is being latched internally, but I do not believe that the during the read operation, the devices use an internal address
latch. However, I might be wrong.

The devices does have 'command mode' whereby it is possible to interrogate the device etc. There is a reset command which I tried to no effect.

Thanks

 

[barry]

The control pins are held high at power up via some programmable logic. This provide address decoding / mapping.

But isn't your programmable logic also powering up at the same time as your flash? Can you rely on the programmable logic to pull the control pins to the proper state while IT'S powering up? Maybe you need some pull-ups/downs...

 

[sh-eda]

I've had to come off looking at it for the moment.
I suspect you are probably correct, and it's very marginal.
I have checked the control lines on the scope and they do go high on power up.

Unfortunately the board I am looking at is a very old design and limited what I can alter.

The programmable logic is an old altera EPLD device. (one time programmable, so is not relying on an an external eeprom to boot from etc.). Firmware wise I have also checked the code and again should alway come up high straight away.

Unfortunately the EPLD outputs can not be configured as open collector or high impedance. I guess as a test I could temporarily disconnect the EPLD, pull the control lines up (via resistors), then reconnect the signals to the EPLD after power up, and see if I am able to address the flash correctly.