Flash ADC issue with effects of DC bias voltage of comparator

[Monady]

in flash adc, if we directly connect reference voltage to the comparator, DC bias voltage of comparator has some effect on reference voltages and causes some fault and we can not have accurate references .how can i solve this problem?

 

[rfsystem]

flash adc -pdf

The only way is to dimensioning the comparator so that the mismatch offset does not violate the DNL spec. That is the reason why power in flash increase by the power of eight

p(flash)~8^n


So you need 2^n comparators and each getting lower acceptable offset voltage by 1/2^n. So the area and the so the power of each comparator increases by (2^n)^2.

So in total

p~(2^n)*(2^n)^2=(2^n)^3=2^(3*n)=(2^3)^n=8^n

 

[taghizadeh100]

Flash ADC

hello
after account fft (fourier components of transient response) how we can account ENOB?
for account INL and DNL it is possible we use of output comparator result(thermometr code) or we must use of binary code ?